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user? manual printed in japan v852 ? 32/16-bit single-chip microcontrollers hardware m pd703002 m pd70p3002 document no. u10038ej3v1um00 (3rd edition) date published december 1997 n cp(k) 1995
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notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. v851, v852, and v850 family are trademarks of nec corporation. windows is either a registered trademark or a trademark of microsoft corporation in the united states and/or other countries. unix is a registered trademark in the united states and other countries, licenced exclusively through x/open company, limited.
the information in this document is subject to change without notice. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m7 96.5 the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative.
nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. cumbica-guarulhos-sp, brasil tel: 011-6465-6810 fax: 011-6465-6829 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 j97. 8
major revisions in this edition (1/2) pages description p.3 1.5 differences between m pd70p3002 and m pd703002 were added. p.6 connection of pins 39 to 41 was changed in 1.6.2 prom programming mode . p.7 v dd , v ss , cv dd , and cv ss pins were added to 1.7.1 internal block diagram . p.14 function in normal operation mode of v dd was modified in 2.1.2 prom programming mode ( m pd70p3002 only) . p.17 description was added to 2.3.1 (4) (b) (vii) txd . p.19 description was added to 2.3.1 (8) (b) (ii) uben . p.24 description was added to 2.4 each pins i/o circuit type and connection when unused . p.52 4.3.2 bus width was added. p.57 description was added to 4.7.1 outline of function . p.64 illustration was modified in 4.8 (7) bus hold timing . p.65 description was added to 4.10.2 data space . p.73 5.2.4 noise elimination from nmi pin was added. p.85 description of id bit function was added to 5.3.8 maskable interrupt status flag . p.93 figure 5-13. pipeline operation upon reception of interrupt request (outline) was modified. p.128 description was modified in 7.4.3 overflow . p.138 value in expression was modified in figure 7-14. pulse width measurement timing (timer 1) . p.140 description was modified in 7.6 (3) (a) using timer 1 . p.140 value in expression in remark was modified in figure 7-17. pwm output timing (tm1) . p.142 contents were modified in figure 7-19. interrupt request processing routine, modifying compare value (timer 1) . p.143 value in expression was modified in figure 7-20. cycle measurement timing (tm1) . p.164 description of crxen bit function was added to 8.3.3 (1) clocked serial interface mode register n (csimn) . p.166 chart was modified in 8.3.4 (1) transfer format . p.168 chart was modified in figure 8-6. timing of 3-wire serial i/o mode (transmission) . p.169 chart was modified in figure 8-7. timing of 3-wire serial i/o mode (reception) . p.170 description was modified in 8.3.7 (1) starting transmission/reception . p.171 chart was modified in figure 8-8. timing of 3-wire serial i/o mode (transmission/ reception) . p.187 description of p20 bit functionwas added in 9.3.3 port 2 .
major revisions in this edition (2/2) pages description p.211 port output latch was modified to port input/output latch in table 10-2. initial values of each register at reset . p.214 description was added to 11.2 (2) output disable mode . p.215 11.3 page programming mode flowchart was modified partially. p.216 description of v pp and v dd was modified in 11.3 page programming mode timing . p.217 part of 11.3 byte programming mode flowchart was modified. p.219 description was modified in 11.4 prom read procedure (1) . p.221 csic1 and csic2 were added to appendix a register index . p.225 appendix b legend (2) symbols used for code was added. p.230 code of satsubi was modified in appendix b instruction set list . the mark shows major revised points.
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introduction readers this manual is intended for users who wish to understand the functions of the v852 ( m pd703002, 70p3002) and design application systems using the v852. purpose this manual presents information on the hardware functions of the v852. organization two volumes of the v852 users manual are available: hardware (this manual) and architecture (v850 family tm users manual - architecture) manuals. the organization of each manual is as follows: hardware architecture ? pin function ? data type ? cpu function ? register set ? internal peripheral function ? instruction format and instruction set ? prom mode ? interrupt and exception ? pipeline operation how to read this manual it is assumed that the readers of this manual have general knowledge on electric engineering, logic circuits, and microcontrollers. ? to find the details of a register where the name is known -> refer to appendix a register index . ? to confirm the details of the function where the name is known -> refer to appendix c index . ? to understand the details of an instruction function -> refer to the v850 family users manual - architecture . ? to understand the overall functions of the v852 -> read this manual according to the table of contents. legend data representation weight : high digits on the left and low digits on the right active low representation : xxx (top bar over pin or signal name) memory map address : top: highest, bottom: lowest note : description of note in the text caution : information requiring particular attention remark : additionally explanatory material numeric representations : binary ... xxxx or xxxxb decimal ... xxxx hexadecimal ... xxxxh prefix indicating power of 2 : k (kilo): 2 10 = 1024 (address space, memory m (mega): 2 20 = 1024 2 capacity) g (giga): 2 30 = 1024 3
related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. documents related to device document name document number japanese english v850 family users manual-architecture u10243j u10243e v850 family instruction list u10229j u10229e m pd703002 data sheet u11826j u11826e m pd70p3002 data sheet u11827j u11827e v852 users manual-hardware u10038j this manual v852 register instruction list u10513j documents related to development tools document name document number japanese english ie-703002-mc (in-circuit emulator) u11595j ca850 (c compiler package) operation unix tm based u11013j u11013e operation windows tm based u11068j u11068e c language u11010j u11010e assembly language u10543j u10543e project manager windows based u11991j u11991e rx850 (real-time os) basic u11037j u11037e technical u11117j u11117e nucleus installation u11038j u11038e debugger windows based u11158j u11158e az850 (system performance analyzer) u11181j u11181e id850 (c source debugger) instruction unix based u12209j installation unix based u12210j u12210e instruction windows based u11196j u11196e
C i C contents chapter 1 introduction ....................................................................................................... 1 1.1 general .............................................................................................................................. 1 1.2 features ............................................................................................................................. 2 1.3 application fields ............................................................................................................ 3 1.4 ordering information ....................................................................................................... 3 1.5 differences between m pd70p3002 and m pd703002 .................................................... 3 1.6 pin configuration (top view) ......................................................................................... 4 1.6.1 normal operation mode ...................................................................................................... 4 1.6.2 prom programming mode ................................................................................................ 6 1.7 function block configuration ........................................................................................ 7 1.7.1 internal block diagram ........................................................................................................ 7 1.7.2 internal units ....................................................................................................................... 8 1.8 differences between v851 and v852 ............................................................................. 10 chapter 2 pin functions ........................................................................................................ 11 2.1 pin function list .............................................................................................................. 11 2.1.1 normal operation mode ...................................................................................................... 11 2.1.2 prom programming mode ( m pd70p3002 only) ............................................................... 14 2.2 pin status .......................................................................................................................... 15 2.3 pin function ..................................................................................................................... 16 2.3.1 normal operation mode ...................................................................................................... 16 2.3.2 prom programming mode ( m pd70p3002 only) ............................................................... 23 2.4 i/o circuit type and connection of unused pins ....................................................... 24 2.5 pin i/o circuits ................................................................................................................. 25 chapter 3 cpu functions ...................................................................................................... 27 3.1 features ............................................................................................................................. 27 3.2 cpu register set ............................................................................................................. 28 3.2.1 program register set ........................................................................................................... 29 3.2.2 system register set ............................................................................................................. 30 3.3 operation modes .............................................................................................................. 32 3.3.1 operation modes ................................................................................................................ 32 3.3.2 specifying operation mode ................................................................................................. 33 3.4 address space ................................................................................................................. 34 3.4.1 cpu address space ............................................................................................................ 34 3.4.2 image (virtual address space) .......................................................................................... 35 3.4.3 wrap-around of cpu address space ................................................................................. 36 3.4.4 memory map ....................................................................................................................... 37 3.4.5 area ............................................................................................................................... ...... 38 3.4.6 external expansion mode ................................................................................................... 45 3.4.7 recommended use of address space ............................................................................... 47 3.4.8 peripheral i/o registers ...................................................................................................... 49 chapter 4 bus control function ..................................................................................... 51 4.1 features ............................................................................................................................. 51
C ii C 4.2 bus control pins .............................................................................................................. 51 4.3 bus access ....................................................................................................................... 52 4.3.1 number of access clocks ................................................................................................... 52 4.3.2 bus width ............................................................................................................................. 52 4.4 memory block function .................................................................................................. 53 4.5 wait function ................................................................................................................... 54 4.5.1 programmable wait function ............................................................................................... 54 4.5.2 external wait function ......................................................................................................... 55 4.5.3 relationships between programmable wait and external wait ......................................... 55 4.6 idle state insertion function .......................................................................................... 56 4.7 bus hold function ........................................................................................................... 57 4.7.1 outline of function .............................................................................................................. 57 4.7.2 bus hold procedure ............................................................................................................ 57 4.7.3 operation in power save mode .......................................................................................... 57 4.8 bus timing ........................................................................................................................ 58 4.9 bus priority ....................................................................................................................... 65 4.10 memory boundary operation condition ...................................................................... 65 4.10.1 program space .................................................................................................................... 65 4.10.2 data space .......................................................................................................................... 65 4.11 internal peripheral i/o interface .................................................................................... 66 chapter 5 interrupt/exception processing function ........................................... 67 5.1 features ............................................................................................................................. 67 5.2 non-maskable interrupt ................................................................................................... 69 5.2.1 accepting operation ............................................................................................................ 70 5.2.2 restore operation ............................................................................................................... 72 5.2.3 np flag ............................................................................................................................... .73 5.2.4 noise elimination for nmi pin ............................................................................................. 73 5.2.5 external interrupt mode register 0 (intm0) ...................................................................... 73 5.3 maskable interrupts ......................................................................................................... 74 5.3.1 block diagram ..................................................................................................................... 75 5.3.2 operation ............................................................................................................................. 75 5.3.3 restore ............................................................................................................................... .77 5.3.4 priorities of maskable interrupts ........................................................................................ 78 5.3.5 interrupt control register (xxicn) ........................................................................................ 82 5.3.6 external interrupt mode registers 1 and 2 (intm1 and intm2) ...................................... 84 5.3.7 in-service priority register (ispr) ...................................................................................... 85 5.3.8 maskable interrupt status flag ............................................................................................ 85 5.4 software exception .......................................................................................................... 86 5.4.1 operation ............................................................................................................................. 86 5.4.2 restore ............................................................................................................................... .87 5.4.3 ep flag ............................................................................................................................... .. 88 5.5 exception trap ................................................................................................................. 88 5.5.1 illegal op code definition .................................................................................................... 88 5.5.2 operation ............................................................................................................................. 89 5.5.3 restore ............................................................................................................................... .90 5.6 priority control ................................................................................................................. 91 5.6.1 priorities of interrupts and exceptions ............................................................................... 91 5.6.2 multiple interrupt processing .............................................................................................. 91
C iii C 5.7 interrupt latency time .................................................................................................... 93 5.8 periods where interrupt is not acknowledged ........................................................... 93 chapter 6 clock generation function .......................................................................... 95 6.1 features ............................................................................................................................. 95 6.2 configuration .................................................................................................................... 95 6.3 selecting input clock ...................................................................................................... 96 6.3.1 direct mode ......................................................................................................................... 96 6.3.2 pll mode ............................................................................................................................ 96 6.4 pll stabilization .............................................................................................................. 98 6.5 power save control ......................................................................................................... 99 6.5.1 general ............................................................................................................................... .99 6.5.2 control registers ................................................................................................................. 101 6.5.3 halt mode ......................................................................................................................... 104 6.5.4 idle mode .......................................................................................................................... 106 6.5.5 software stop mode ......................................................................................................... 108 6.6 specifying oscillation stabilization time .................................................................... 110 6.7 clock output control ...................................................................................................... 113 chapter 7 timer/counter function (real-time pulse unit) ................................... 115 7.1 features ............................................................................................................................. 11 5 7.2 basic configuration ......................................................................................................... 116 7.2.1 timer 1 ............................................................................................................................... . 118 7.2.2 timer 4 ............................................................................................................................... . 120 7.3 control registers ............................................................................................................. 121 7.4 timer 1 operation ............................................................................................................ 127 7.4.1 count operation .................................................................................................................. 127 7.4.2 selecting count clock frequency ........................................................................................ 127 7.4.3 overflow .............................................................................................................................. 1 28 7.4.4 clearing/starting timer by tclr1 input ............................................................................. 129 7.4.5 capture operation ............................................................................................................... 130 7.4.6 compare operation ............................................................................................................. 132 7.5 timer 4 operation ............................................................................................................ 134 7.5.1 count operation .................................................................................................................. 134 7.5.2 selecting the count clock frequency .................................................................................. 134 7.5.3 overflow .............................................................................................................................. 1 34 7.5.4 compare operation ............................................................................................................. 135 7.6 application examples ..................................................................................................... 137 7.7 note ............................................................................................................................... ..... 145 chapter 8 serial interface function ............................................................................ 147 8.1 features ............................................................................................................................. 14 7 8.2 asynchronous serial interface (uart) ........................................................................ 148 8.2.1 features .............................................................................................................................. 1 48 8.2.2 configuration of asynchronous serial interface ................................................................. 149 8.2.3 mode registers and control registers ................................................................................. 151 8.2.4 interrupt request ................................................................................................................. 157 8.2.5 operation ............................................................................................................................. 15 8
C iv C 8.3 clocked serial interface 0 to 2 (csi0 to csi2) ............................................................ 162 8.3.1 features .............................................................................................................................. 1 62 8.3.2 configuration ....................................................................................................................... 163 8.3.3 mode registers and control registers ................................................................................. 164 8.3.4 basic operation ................................................................................................................... 166 8.3.5 transmission in 3-wire serial i/o mode ............................................................................. 168 8.3.6 reception in 3-wire serial i/o mode .................................................................................. 169 8.3.7 transmission/reception in 3-wire serial i/o mode ............................................................ 170 8.3.8 system configuration example .......................................................................................... 172 8.4 baud rate generator 0, 1 (brg0, brg1) ..................................................................... 173 8.4.1 configuration and function ................................................................................................. 173 8.4.2 baud rate generator register 0, 1 (brg0, brg1) ............................................................ 176 8.4.3 baud rate generator prescaler mode register 0, 1 (bprm0, bprm1) ............................ 176 chapter 9 port function ...................................................................................................... 177 9.1 features ............................................................................................................................. 17 7 9.2 basic configuration of port ........................................................................................... 178 9.3 port pin function ............................................................................................................. 182 9.3.1 port 0 ............................................................................................................................... .... 182 9.3.2 port 1 ............................................................................................................................... .... 186 9.3.3 port 2 ............................................................................................................................... .... 187 9.3.4 port 3 ............................................................................................................................... .... 192 9.3.5 port 4 ............................................................................................................................... .... 197 9.3.6 port 5 ............................................................................................................................... .... 199 9.3.7 port 6 ............................................................................................................................... .... 201 9.3.8 port 9 ............................................................................................................................... .... 202 9.3.9 port 10 ............................................................................................................................... .. 205 9.4 noise elimination circuit ................................................................................................ 208 chapter 10 reset function .................................................................................................... 209 10.1 features ............................................................................................................................. 20 9 10.2 pin function ..................................................................................................................... 209 10.3 initialize ............................................................................................................................. 21 0 chapter 11 prom mode ............................................................................................................. 213 11.1 prom mode ...................................................................................................................... 213 11.2 operation mode ................................................................................................................ 213 11.3 prom write procedure ................................................................................................... 215 11.4 prom read procedure ................................................................................................... 219 11.5 screening of otprom version ..................................................................................... 220 11.6 caution on stop mode release when using external clock .................................. 220 appendix a register index ..................................................................................................... 221 appendix b instruction set list .......................................................................................... 225 appendix c index ......................................................................................................................... 233
C v C list of figures (1/2) figure no. title page 3-1. program counter (pc) ......................................................................................................... 29 3-2. interrupt source register (ecr) ......................................................................................... 30 3-3. program status word (psw) .............................................................................................. 31 3-4. cpu address space ............................................................................................................ 34 3-5. image on address space .................................................................................................... 35 3-6. interrupt/exception table ..................................................................................................... 39 3-7. external memory area (when expanded to 64 kb, 256 kb, or 1 mb) .............................. 42 3-8. external memory area (when expanded to 4 mb) ............................................................. 43 3-9. external memory area (when fully expanded) ................................................................... 44 3-10. recommended memory map ............................................................................................... 48 4-1. example of inserting wait states ........................................................................................ 55 5-1. non-maskable interrupt processing .................................................................................... 70 5-2. accepting non-maskable interrupt request ....................................................................... 71 5-3. reti instruction processing ................................................................................................ 72 5-4. maskable interrupt block diagram ...................................................................................... 75 5-5. maskable interrupt processing ............................................................................................ 76 5-6. reti instruction processing ................................................................................................ 77 5-7. example of interrupt nesting process ................................................................................ 79 5-8. example of processing interrupt requests simultaneously generated ........................... 81 5-9. software exception processing ........................................................................................... 86 5-10. reti instruction processing ................................................................................................ 87 5-11. exception trap processing .................................................................................................. 89 5-12. reti instruction processing ................................................................................................ 90 5-13. pipeline operation upon reception of interrupt request (outline) ................................... 93 6-1. block configuration .............................................................................................................. 112 7-1. basic operation of timer 1 .................................................................................................. 127 7-2. operation after occurrence of overflow (when eclr1 = 0, ost = 1) ............................ 128 7-3. clearing/starting timer by tclr1 input (when eclr1 = 1, ost = 0) ............................ 129 7-4. relationships between clear/start by tclr1 input and overflow (when eclr1 = 1, ost = 1) ............................................................................................... 129 7-5. example of tm1 capture operation (when both edges are specified) ............................. 130 7-6. example of tm1 capture operation ................................................................................... 131 7-7. example of compare operation .......................................................................................... 132 7-8. example of tm1 compare operation (set/reset output mode) ......................................... 133 7-9. basic operation of timer 4 .................................................................................................. 134 7-10. operation with cm4 at 1 to ffffh ..................................................................................... 135 7-11. when cm4 is set to 0 ......................................................................................................... 136 7-12. example of timing of interval timer operation (timer 4) .................................................. 137 7-13. setting procedure of interval timer operation (timer 4) .................................................... 137
C vi C list of figures (2/2) figure no. title page 7-14. pulse width measurement timing (timer 1) ....................................................................... 138 7-15. setting procedure for pulse width measurement (timer 1) ............................................... 139 7-16. interrupt request processing routine calculating pulse width (timer 1) ........................ 139 7-17. pwm output timing (tm1) .................................................................................................. 140 7-18. programming procedure of pwm output (timer 1) ............................................................ 141 7-19. interrupt request processing routine, modifying compare value (timer 1) .................... 142 7-20. cycle measurement timing (tm1) ...................................................................................... 143 7-21. set-up procedure for cycle measurement (timer 1) .......................................................... 144 7-22. interrupt request processing routine calculating cycle (timer 1) ................................... 144 8-1. block diagram of asynchronous serial interface ............................................................... 150 8-2. format of transmit/receive data of asynchronous serial interface ................................ 158 8-3. asynchronous serial interface transmission completion interrupt timing ...................... 159 8-4. asynchronous serial interface reception completion interrupt timing ........................... 161 8-5. receive error timing ........................................................................................................... 161 8-6. timing of 3-wire serial i/o mode (transmission) ............................................................... 168 8-7. timing of 3-wire serial i/o mode (reception) ..................................................................... 169 8-8. timing of 3-wire serial i/o mode (transmission/reception) ............................................... 171 8-9. example of csi system configuration ................................................................................ 171 8-10. block diagram of baud rate generator ............................................................................. 172 9-1. block diagram of p00, p01 (port 0) .................................................................................... 183 9-2. block diagram of p02 to p07 (port 0) ................................................................................ 183 9-3. block diagram of p10 to p17 (port 1) ................................................................................ 186 9-4. block diagram of p20 (port 2) ............................................................................................ 188 9-5. block diagram of p21 to p24 (port 2) ................................................................................ 188 9-6. block diagram of p25 (port 2) ............................................................................................ 189 9-7. block diagram of p26 (port 2) ............................................................................................ 189 9-8. block diagram of p27 (port 2) ............................................................................................ 190 9-9. block diagram of p30, p33, p35 (port 3) ........................................................................... 193 9-10. block diagram of p31, p36 (port 3) .................................................................................... 194 9-11. block diagram of p32, p37 (port 3) .................................................................................... 194 9-12. block diagram of p34 (port 3) ............................................................................................ 195 9-13. block diagram of p40 to p47 (port 4) ................................................................................ 197 9-14. block diagram of p50 to p57 (port 5) ................................................................................ 199 9-15. block diagram of p60 to 67 (port 6) ................................................................................... 202 9-16. block diagram of p90 to p97 (port 9) ................................................................................ 203 9-17. block diagram of p100, p103 (port 10) ............................................................................. 205 9-18. block diagram of p101 (port 10) ........................................................................................ 206 9-19. block diagram of p102 (port 10) ........................................................................................ 206 9-20. example of noise elimination timing ................................................................................. 208 11-1. prom read timing ............................................................................................................. 219
C vii C list of tables table no. title page 1-1. differences between m pd70p3002 and m pd70p3002 ....................................................... 3 1-2. differences between v851 and v852 ................................................................................. 10 3-1. program registers ............................................................................................................... 29 3-2. system register numbers ................................................................................................... 30 4-1. bus priority ........................................................................................................................... 65 5-1. interrupt list .......................................................................................................................... 68 5-2. addresses and bits of interrupt control register ............................................................... 83 6-1. operation of clock generator by power save control ...................................................... 100 6-2. operating status in halt mode ......................................................................................... 104 6-3. operating status in idle mode .......................................................................................... 106 6-4. operating status in software stop mode ......................................................................... 108 6-5. example of count time ....................................................................................................... 112 7-1. configuration of rpu ........................................................................................................... 116 7-2. capture trigger signal to 16-bit capture register (tm1) ................................................. 130 7-3. interrupt request signal from 16-bit compare register (tm1) ........................................ 132 8-1. default priority of interrupts ................................................................................................. 157 8-2. brg set-up values .............................................................................................................. 174 10-1. operating status of each pin during reset period ........................................................... 209 10-2. initial values of each register at reset ............................................................................. 211
C viii C [memo]
1 chapter 1 introduction chapter 1 introduction the v852 is a product of necs v850 family of single-chip microcontrollers for real-time control applications. this chapter briefly outlines the v852. 1.1 general the v852 is a 32-/16-bit single-chip microcontroller that employs the cpu core of the v850 family of high- performance 32-bit single-chip microcontrollers for real-time control applications, and integrates peripheral functions such as rom/ram, real-time pulse unit, and serial interface. the v852 is provided with multiplication instructions that are executed with a hardware multiplier, saturated operation instructions, and bit manipulation instructions that are ideal for digital servo control applications, in addition to basic instructions that have a high real-time response speed and can be executed in 1 clock cycle. this microcontroller can be applied as a real-time control system to numerous fields such as the av field (camcorders, vcrs, etc.), oa field (ppcs, lbps, printers, etc.), industrial field (motor control, nc machine tools, etc.), and communication field (cellular phones, etc.). in any of these applications, the v852 demonstrates an extremely high cost effectiveness.
2 chapter 1 introduction 1.2 features number of instructions : 74 minimum instruction execution time : 40 ns (at 25 mhz) general register : 32 bits x 32 instruction set : signed multiply (16 bits x 16 bits -> 32 bits): 1 to 2 clocks saturated operation instructions (with overflow/underflow detection function) 32-bit shift instructions: 1 clock bit manipulation instructions load/store instructions with long/short format memory space : 16 mb linear (common to program/data) memory is divided in 1 mb unit blocks and wait states can be inserted into a bus cycle for every two blocks. programmable wait function idle state insertion function external bus interface : 16-bit data bus (address/data multiplexed) bus hold function external wait function internal memory : rom/prom : 90 kb ram : 3 kb interrupt/exception : non-maskable: 1 source maskable: 16 sources (eight levels of priorities can be set.) illegal instruction code exception i/o line : i/o port : 67 real-time pulse unit : 16-bit timer/event counter: 1 ch 16-bit capture/compare register: 4 16-bit interval timer: 1 ch 16-bit compare register: 1 serial interface : asynchronous serial interface (uart): 1 ch clocked serial interface (csi): 3 ch dedicated baud rate generator clock generator : multiplication function by pll clock synthesizer power save function : halt/idle/stop mode clock output stop function cmos technology
3 chapter 1 introduction 1.3 application fields av field : camcorders, vcrs, etc. oa field : ppcs, lbps, printers, etc. industrial field : motor control, nc machine tools, etc. communication field : cellular phones, etc. 1.4 ordering information part number package internal rom m pd703002gc-25-xxx-7ea 100-pin plastic qfp (fine pitch) (14 x 14 mm) mask rom m pd70p3002gc-25-7ea 100-pin plastic qfp (fine pitch) (14 x 14 mm) one-time prom remark xxx indicates a rom code suffix. 1.5 differences between m pd70p3002 and m pd703002 the m pd70p3002 is a prom version of the m pd703002. therefore, these two versions are identical except for differences because of the rom specifications (for example, specifications concerning writing and verifying). table 1-1 and 1-2 show the differences between the two. table 1-1. differences between m pd70p3002 and m pd703002 item part number m pd70p3002 m pd703002 internal program memory one-time prom mask rom (electrical writing) (can be written only once) prom programming pin provided none setting of mode0 and ? in normal operation mode ? in normal operation mode mode1 pins mode0, 1 = lh mode0, 1 = lh ? in prom programming mode ? in rom-less mode mode0, 1 = hh mode0, 1 = ll electrical characteristics supply current, recommended oscillation circuit, etc. are different. internal rom empty area when programming the internal rom, write the same instruction code for the empty area of the prom and mask rom versions. others noise immunity and noise radiation differ because circuit scale and mask layout differ. cautions 1. the prom and mask rom versions differ from each other in terms of noise immunity and noise emission. when replacing the prom version with the mask rom version in the course of switching from experimental production to mass production, perform thorough evalua- tion with the cs model (not es model) of the mask rom version. 2. directly connect the mode0 and mode1 pins to v dd or v ss . remark l : low level h : high level
4 chapter 1 introduction 1.6 pin configuration (top view) 1.6.1 normal operation mode ? m pd703002gc-25-xxx-7ea ? m pd70p3002gc-25-7ea caution the content in parentheses indicates the processing of the pin not used in the normal operation mode. g: connect this pin to v ss . 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 p64/a20 p63/a19 p62/a18 p61/a17 p60/a16 v ss v dd p57/ad15 p56/ad14 p55/ad13 p54/ad12 p53/ad11 p52/ad10 p51/ad9 p50/ad8 v dd v ss p47/ad7 p46/ad6 p45/ad5 p44/ad4 p43/ad3 p42/ad2 p41/ad1 p40/ad0 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 p07/intp13 p06/intp12 p05/intp11 p04/intp10 p03/ti1 p02/tclr1 p01/to11 p00/to10 v dd v ss p17 p16 p15 p14 p13 p12 p11 p10 v ss v dd mode0 mode1 ic0(g) pllsel reset 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 v ss v dd p90/lben p91/uben p92/r/w p93/dstb p94/astb p95/st0 p96/st1 p97 wait v dd v ss x2 x1 cksel cv dd cv ss clkout v ss v dd p103 p102 p101/hldrq p100/hldak 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 p65/a21 p66/a22 p67/a23 v ss v dd p30/so0 p31/si0 p32/sck0 p33/txd p34/rxd p35/so1 p36/si1 p37/sck1 v dd v ss p20/nmi p21/intp00 p22/intp01 p23/intp02 p24/intp03 p25/so2 p26/si2 p27/sck2 v ss v dd
5 chapter 1 introduction p00 to p07 : port0 p10 to p17 : port1 p20 to p27 : port2 p30 to p37 : port3 p40 to p47 : port4 p50 to p57 : port5 p60 to p67 : port6 p90 to p97 : port9 p100 to p103 : port10 to10, to11 : timer output tclr1 : timer clear ti1 : timer input intp00 to intp03, intp10 to intp13 : interrupt request from peripherals nmi : non-maskable interrupt request so0 to so2 : serial output si0 to si2 : serial input sck0 to sck2 : serial clock txd : transmit data rxd : receive data ad0 to ad15 : address/data bus a16 to a23 : address bus lben : lower byte enable uben : upper byte enable r/w : read/write status dstb : data strobe astb : address strobe st0, st1 : status hldak : hold acknowledge hldrq : hold request clkout : clock output cksel : clock select pllsel : pll select wait : wait mode0, mode1 : mode reset : reset x1, x2 : crystal cv dd : clock generator power supply cv ss : clock generator ground v dd : power supply v ss : ground ic0 : internally connected
6 chapter 1 introduction 1.6.2 prom programming mode ? m pd70p3002gc-25-7ea caution the content in parentheses indicates the connection of the pin not used in the prom programming mode. l : individually connect this pin to v ss via a resistor. h : connect this pin to v dd via a resistor. g : connect this pin to v ss . v : connect this pin to v dd . open : connect nothing to this pin. a0 to a16 : address bus d0 to d7 : data bus ce : chip enable oe : output enable pgm : programming mode mode0, mode1 : programming mode set v dd : power supply v ss : ground v pp : programming power supply 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 a4 a3 a2 a1 a0 v ss v dd a16 a15 a14 a13 a12 a11 a10 a8 v dd v ss d7 d6 d5 d4 d3 d2 d1 d0 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 v ss v dd h v dd v ss (open) (g) (v) (v) (g) (open) v ss v dd (l) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 a5 a6 a7 v ss v dd (l) v dd v ss a9 (l) ce oe pgm v ss v dd (l) v dd v ss (l) v ss v dd mode0 mode1 v pp (v) (g) (l)
7 chapter 1 introduction 1.7 function block configuration 1.7.1 internal block diagram note pins used in the prom programming mode astb dstb r/w uben lben wait intc rpu to10, to11 tclr1 ti1 uart brg0 csi0 txd rxd so0 si0 sck0 pc 32-bit barrel shifter system register general register 32 bits x 32 3-kb ram rom cpu bcu cg port instruction queue a16 to a23 ad0 to ad15 st0, st1 ce oe pgm v pp v dd v ss cv dd cv ss hldrq hldak d0 to d7 a0 to a16 cksel pllsel clkout x1 x2 reset mode0, mode1 nmi intp00 to intp03 intp10 to intp13 sio alu p100 to p103 p90 to p97 p60 to p67 p50 to p57 p40 to p47 p30 to p37 p21 to p27 p20 p10 to p17 p00 to p07 rom/ prom 90-kb multiplier 16x16 -> 32 csi1 brg1 csi2 so2 si2 sck2 so1 si1 sck1 note
8 chapter 1 introduction 1.7.2 internal units (1) cpu executes almost all the instruction processing such as address calculation, arithmetic/logic operation, and data transfer in 1 clock by using a 5-stage pipeline. dedicated hardware devices such as a multiplier (16 bits x 16 bits -> 32 bits) and a barrel shifter (32 bits) are provided to increase the speed of processing complicated instructions. (2) bus control unit (bcu) initiates the necessary number of external bus cycles based on the physical address obtained by the cpu. if the cpu does not issue a request to start a bus cycle when fetching an instruction from the external memory area, generates a prefetch address to prefetch an instruction code. the prefetched instruction code is loaded to the internal instruction queue. (3) rom/prom rom or prom of 90 kbytes mapped starting from address 00000000h. access is enabled/disabled by the mode0 and mode1 pins. with the prom version, the programming mode is specified by these two pins. this rom/prom is accessed in 1 clock by the cpu when an instruction is fetched. (4) ram 3-kb ram mapped starting from address ffffe000h. this ram can be accessed in 1 clock by the cpu when data is accessed. (5) interrupt controller (intc) processes interrupt requests (nmi, intp00 to intp03, intp10 to intp13) from the internal peripheral hardware and external sources. eight levels of priorities can be specified for these interrupt requests, and multiplexed processing control can be performed on an interrupt source. (6) clock generator (cg) supplies the cpu clock whose frequency is one or five times (when the internal pll is used) or 1/2 times (when the pll is not used) the frequency of the oscillator connected across the x1 and x2 pins. input from an external clock source can also be referenced instead of using the oscillator. (7) real-time pulse unit (rpu) provides a 16-bit timer/event counter, a 16-bit interval timer, and capabilities for measuring pulse width and frequency, and generation of programmable pulse outputs. (8) serial interface (sio) the serial interface of the v852 consists of 1-channel asynchronous serial interface (uart) and 3-channel synchronous or clocked serial interface (csi). uart transfers data by using the txd and rxd pins, and the csi transfers data by using the so0 to so2, si0 to si2, and sck0 to sck2 pins. the output of the baud rate generator and system clock can be selected as the serial interface clock source.
9 chapter 1 introduction (9) ports the v852 is provided with a total of 68 i/o port pins (one of them is input only) that constitute ports 0 to 10. these port pins also function as various control pins. port i/o function port0 8-bit i/o general port timer i/o, external interrupt port1 C port2 external interrupt, serial interface port3 serial interface port4 external address/data bus port5 port6 external address bus port9 external bus interface control signal i/o port10 4-bit i/o
10 chapter 1 introduction 1.8 differences between v851? and v852 the v852 is provided with increased internal rom/ram capacity and more csi channels of the serial interface. the number of pll multiplication can be selected from either one or five. table 1-2. differences between v851 and v852 item v851 v852 internal rom capacity 32 kb 90 kb internal ram capacity 1 kb 3 kb serial interface uart : 1 ch uart : 1 ch csi : 1 ch csi : 3 ch baud rate generator : 1 baud rate generator : 2 interrupt source external : 9 sources (including nmi) external : 9 sources (including nmi) internal : 10 sources internal : 12 sources interrupt/ 00000160h intcsi1 exception table 00000170h intcsi2 number of multiplication multiplication by 5 multiplication by 1 or 5 when using pll i/o port (total 68) dedicated pins : 17 dedicated pins : 11 shared with control pins : 51 shared with control pins : 57 pin name (at normal operation mode) qfp pin number 52 ic1 pllsel 78 p27 p27/sck2 79 p26 p26/si2 80 p25 p25/so2 88 p37 p37/sck1 89 p36 p36/si1 90 p35 p35/so1 93 p32/sck p32/sck0 94 p31/si p31/si0 95 p30/so p30/so0 peripheral i/o register i/o address fffff094h brg1 fffff096h bprm1 fffff098h csim1 fffff09ah sio1 fffff0a8h csim2 fffff0aah sio2 fffff11ch csic1 fffff11eh csic2
11 chapter 2 pin functions chapter 2 pin functions the following table shows the names and functions of the v852s pins. these pins can be divided by function into port pins and other pins. 2.1 pin function list 2.1.1 normal operation mode (1) port pins (1/2) pin name i/o function alternate function p00 i/o to10 p01 to11 p02 tclr1 p03 ti1 p04 intp10 p05 intp11 p06 intp12 p07 intp13 p10 to p17 i/o C p20 input nmi p21 i/o intp00 p22 intp01 p23 intp02 p24 intp03 p25 so2 p26 si2 p27 sck2 port 0. 8-bit i/o port. can be specified in input/output mode in 1-bit units. port 1. 8-bit i/o port. can be specified in input/output mode in 1-bit units. port 2. p20 is an input-only port. operates as an nmi input when a valid edge is input. indicates nmi input status with bit 0 of p2 register. p21 to p27 are 7-bit i/o ports. input/output can be specified in 1-bit units.
12 chapter 2 pin functions (2/2) pin name i/o function alternate function p30 i/o so0 p31 si0 p32 sck0 p33 txd p34 rxd p35 so1 p36 si1 p37 sck1 p40 to 47 i/o ad0 to ad7 p50 to p57 i/o ad8 to ad15 p60 to p67 i/o port 6. a16 to a23 8-bit i/o port. can be specified in input/output mode in 1-bit units. p90 i/o lben p91 uben p92 r/w p93 dstb p94 astb p95 st0 p96 st1 p97 C p100 i/o hldak p101 hldrq p102 C p103 C port 3. 8-bit i/o port. can be specified in input/output mode in 1-bit units. port 4. 8-bit i/o port. can be specified in input/output mode in 1-bit units. port 5. 8-bit i/o port. can be specified in input/output mode in 1-bit units. port 9. 8-bit i/o port. can be specified in input/output mode in 1-bit units. port 10. 4-bit i/o port. can be specified in input/output mode in 1-bit units.
13 chapter 2 pin functions external clear signal input to timer 1. external count clock input to timer 1. external capture trigger input to timer 1. also used to input external maskable interrupt request. (2) non-port pins (1/2) pin name i/o function alternate function to10 output pulse signal output from timer 1. p00 to11 p01 tclr1 input p02 ti1 p03 intp10 input p04 intp11 p05 intp12 p06 intp13 p07 nmi input non-maskable interrupt request input. p20 intp00 input external maskable interrupt request input. p21 intp01 p22 intp02 p23 intp03 p24 so0 output serial transmit data output from csi0. p30 si0 input serial receive data input to csi0. p31 sck0 i/o serial clock i/o from/to csi0. p32 so1 output serial transmit data output from csi1. p35 si1 input serial receive data input to csi1. p36 sck1 i/o serial clock i/o from/to csi1. p37 so2 output serial transmit data output from csi2. p25 si2 input serial receive data input to csi2. p26 sck2 i/o serial clock i/o from/to csi2. p27 txd output serial transmit data output from uart. p33 rxd input serial receive data input to uart. p34 ad0 to ad7 i/o 16-bit multiplexed address/data bus when external memory is used. p40 to p47 ad8 to ad15 p50 to p57 a16 to a23 o higher address bus when external memory is used. p60 to p67 lben output lower byte enable signal output of external data bus. p90 uben higher byte enable signal output of external data bus. p91 r/w external read/write status output. p92 dstb external data strobe signal output. p93 astb external address strobe signal output. p94 st0 external bus cycle status output. p95 st1 p96 hldak output bus hold acknowledge output. p100 hldrq input bus hold request input. p101 clkout output system clock output. C
14 chapter 2 pin functions (2/2) pin name i/o function alternate function cksel input input specifying operation mode of clock generator. C pllsel input input specifying the number of pll multiplication. C wait input control signal input inserting wait state to bus cycle. C mode0, mode1 input specifies operation mode of the v852. C reset input system reset input. C x1 input system clock oscillator connecting pins. supply external clock to x1. C x2 C C cv dd C positive power supply for internal clock generator. C cv ss C ground for internal clock generator. C v dd C positive power supply C v ss C ground C ic0 C internally connected C 2.1.2 prom programming mode ( m pd70p3002 only) control and timing of the v852 in the prom mode are compatible with those of the m pd27c1001a. the functions of the pins of the v852 in the prom mode are as follows: pin name function in prom mode function in normal operation mode a0 to a7 address input, low (a0 to a7) p60 to p67 a8, a9, a10 to a16 address input, high (a8 to a16) p50, p20, p51 to p57 d0 to d7 data input/output p40 to p47 ce ce (chip enable) input p25 oe oe (output enable) input p26 pgm pgm (program) input p27 v pp power supply for program write ic0 mode0, mode1 operation mode specification mode0, mode1
15 chapter 2 pin functions 2.2 pin status the operating status of each pin in each operation mode is as follows: ad0 to ad15 hi-z hi-z hi-z hi-z hi-z hi-z a16 to a23 hi-z hi-z hi-z hi-z retained note 1 retained lben, uben hi-z hi-z hi-z hi-z retained note 1 retained r/w hi-z hi-z hi-z hi-z h h dstb hi-z hi-z hi-z hi-z h h astb hi-z hi-z hi-z hi-z h h st0, st1 hi-z hi-z hi-z hi-z idle status idle status hldrq C C C operates operates operates hldak hi-z hi-z hi-z l operates operates wait C CCCCC clkout operates l l operates note 2 operates note 2 operates note 2 hi-z : high-impedance retained : retains status in external bus cycle immediately before l : low-level output h : high-level output C : input not sampled notes 1. undefined immediately after bus hold ends. 2. l during clock output inhibit mode. stop mode idle mode bus hold reset operating status pin idle state halt mode
16 chapter 2 pin functions 2.3 pin function 2.3.1 normal operation mode (1) p00 to p07 (port0) ... 3-state i/o these pins constitute an 8-bit i/o port, port 0. they also serve as control signal pins. p00 to p07 function not only as i/o port pins, but also as the i/o pins of the real-time pulse unit (rpu) and external interrupt request input pins. each bit of port 0 can be specified in the port or control mode, by using port mode control register 0 (pmc0). (a) port mode p00 to p07 can be set in the input or output mode in 1-bit units by using port mode register 0 (pm0). (b) control mode p00 to p07 can be set in the port or control mode in 1-bit units by the pmc0 register. (i) to10, to11 (timer output) ... output these pins output pulse signals from timer 1. (ii) tclr1 (timer clear) ... input this pin inputs an external clear signal to timer 1. (iii) ti1 (timer input) ... input this pin inputs an external count clock to timer 1. (iv) intp10 to intp13 (interrupt request from peripherals) ... input these pins are the external interrupt request input pins of timer 1. (2) p10 to p17 (port 1) ... 3-state i/o these pins constitute an 8-bit i/o port, port 1, which can be set in the input or output mode in 1-bit units by using port mode register 1 (pm1). the pins of port 1 function only as i/o pins and are not multiplexed with control pins. (3) p20 to p27 (port 2) ... 3-state i/o these pins constitute an i/o port, port 2, which can be set in the input or output mode in 1-bit units except p20 which is fixed to the input mode. they function not only as port pins but also as external interrupt input and serial interface (csi) pins. each bit of this port can be specified in the port or control mode by using port mode control register 2 (pmc2). (a) port mode p21 to p27 can be set in the input or output mode in 1-bit units by port mode register 2 (pm2). pm20 is an input-only port, and operates as an nmi input when a valid edge is input. (b) control mode p21 to p27 can be set in the port or control mode in 1-bit units by port mode control register 2 (pmc2). p20 is dedicated to the control mode.
17 chapter 2 pin functions (i) nmi (non-maskable interrupt request) ... input this pin inputs a non-maskable interrupt request. (ii) intp00 to intp03 (interrupt request from peripherals) ... input these pins input external maskable interrupt requests. (iii) so2 (serial output) ... output this pin outputs the serial transmit data of csi2. (iv) si2 (serial input) ... input this pin inputs the serial receive data of csi2. (v) sck2 (serial clock) ... 3-state i/o this pin inputs/outputs the serial clock of csi2. (4) p30 to p37 (port 3) ... 3-state input these pins constitute an 8-bit i/o port, port 3. they also function as control signal pins. p30 to p37 function not only as i/o port pins but also as serial interface (uart, csi) i/o pins in the control mode. (a) port mode p30 to p37 can be set in the input or output mode in 1-bit units by port mode register 3 (pm3). (b) control mode p30 to p37 can be set in the port or control mode in 1-bit units by the pmc3 register. (i) so0 (serial output) ... output this pin outputs the serial transmit data of csi0. (ii) si0 (serial input) ... input this pin inputs the serial receive data of csi0. (iii) sck0 (serial clock) ... 3-state i/o this pin inputs/outputs the serial clock of csi0. (iv) so1 (serial output) ... output this pin outputs the serial transmit data of csi1. (v) si1 (serial input) ... input this pin inputs the serial receive data of csi1. (vi) sck1 (serial clock) ... 3-state i/o this pin inputs/outputs the serial clock of csi1. (vii) txd (transmit data) ... output this pin outputs the serial transmit data of uart. transmit disabled : high-impedance transmit enabled : high-level
18 chapter 2 pin functions (viii) rxd (receive data) ... input this pin inputs the serial receive data of uart. (5) p40 to p47 (port 4) ... 3-state i/o these pins constitute an 8-bit i/o port, port 4. they also form a portion of the address/data bus connected to external memory. p40 to p47 function not only as i/o port pins but also as multiplexed address/data bus pins (ad0 to ad7) in the control mode (external expansion mode) when an external memory is connected. each bit of this port can be set in the port or control mode, in 1-bit units, by using mode specification pins (mode0 and mode1), and memory expansion mode register (mm). (a) port mode p40 to p47 can be set in the input or output port mode in 1-bit units by using port mode register 4 (pm4). (b) control mode (external expansion mode) p40 to p47 can be specified as ad0 to ad7 by using the mode0 and mode1 pins and mm register. (i) ad0 to ad7 (address/data0 to 7) ... 3-state i/o these pins constitute a multiplexed address/data bus when the external memory is accessed. they function as the a0 to a7 output pins of a 24-bit address in the address timing (t1 state), and as the lower 8-bit data i/o bus pins of 16-bit data in the data timing (t2, tw, t3). the output status of these pins changes in synchronization with the rising edge of the clock in each state of the bus cycle. ad0 to ad7 go into a high-impedance state in the idle state (ti). (6) p50 to p57 (port 5) ... 3-state i/o these pins constitute an 8-bit i/o port, port 5. they also form a portion of the address/data bus connected to external memory. p50 to p57 function not only as i/o port pins but also as multiplexed address/data bus pins (ad8 to ad15) in the control mode (external expansion mode) when an external memory is connected. each bit of this port can be set in the port or control mode in 1-bit units by using mode specification pins (mode0 and mode1), and memory expansion mode register (mm). (a) port mode p50 to p57 can be set in the input or output port mode in 1-bit units by using port mode register 5 (pm5). (b) control mode (external expansion mode) p50 to p57 can be specified as ad8 to ad15 by using the mode0 and mode1 pins and mm register. (i) ad8 to ad15 (address/data8 to 15) ... 3-state i/o these pins constitute a multiplexed address/data bus when the external memory is accessed. they function as the a8 to a15 output pins of a 24-bit address in the address timing (t1 state), and as the higher 8-bit data i/o bus pins of 16-bit data in the data timing (t2, tw, t3). the output status of these pins changes in synchronization with the rising edge of the clock in each state of the bus cycle. ad8 to ad15 go into a high-impedance state in the idle state (ti).
19 chapter 2 pin functions (7) p60 to p67 (port 6) ... 3-state i/o these pins constitute an 8-bit i/o port, port 6. they also form a portion of the address/data bus connected to external memory. p60 to p67 function not only as i/o port pins but also as address bus pins (a16 to a23) in the control mode (external expansion mode) when an external memory is connected. this port can be set in the port or control mode in 2-bit units by using mode specification pins (mode0 and mode1), and memory expansion mode register (mm). (a) port mode p60 to p67 can be set in the input or output port mode in 1-bit units by using port mode register 6 (pm6). (b) control mode (external expansion mode) p60 to p67 can be specified as a16 to a23 by using the mode0 and mode1 pins and mm register. (i) a16 to a23 (address/data16 to 23) ... output these pins constitute the higher 8 bits of a 24-bit address bus when the external memory is accessed. the output status of these pins changes in synchronization with the rising edge of the clock in the t1 state. during the idle state (ti), the address of the bus cycle immediately before entering the idle state is retained. (8) p90 to p97 (port 9) ... 3-state i/o these pins constitute an 8-bit i/o port, port 9, and are also used to output control signals. p90 to p96 function not only as i/o port pins but also as control signal output pins in the control mode (external expansion mode) when an external memory is used. this port can be set in the port or control mode in 5-, 2-, or 1-bit units by using mode specification pins (mode0 and mode1), and memory expansion mode register (mm). p97 functions only as i/o pin and is not multiplexed with control pin. (a) port mode p90 to p97 can be set in the input or output port mode in 1-bit units by using port mode register 9 (pm9). (b) control mode (external expansion mode) p90 to p96 can be used to output control signals when so specified by the mode0 and mode1 pins and mm register when an external memory is used. (i) lben (lower byte enable) ... output this is the lower byte enable signal of the 16-bit external data bus. this signal changes in synchronization with the rising edge of the clock in the t1 state of the bus cycle. during the idle state (ti), the address of the bus cycle immediately before entering the idle state is retained. (ii) uben (upper byte enable) ... output this is the upper byte enable signal of the 16-bit external data bus. it becomes active (low) in the odd-number byte access mode, and becomes inactive (high) in the even-number byte access mode. this signal changes in synchronization with the rising edge of the clock in the t1 state of the bus cycle. during the idle state (ti), the address of the bus cycle immediately before entering the idle state is retained.
20 chapter 2 pin functions access uben lben a0 word access 0 0 0 half-word access 0 0 0 byte access even address 1 0 0 odd address 0 1 1 (iii) r/w (read/write status) ... output this is a status signal that indicates whether the bus cycle for external access is a read or write cycle. it goes high in the read cycle and low in the write cycle. this signal changes in synchronization with the rising edge of the clock in the t1 state of the bus cycle. it goes high in the idle state (ti). (iv) dstb (data strobe) ... output this is the access strobe signal of the external data bus. it becomes active (low) in the t2 or tw state of the bus cycle, and becomes inactive (high) in the idle state (ti). (v) astb (address strobe) ... output this is the latch strobe signal of the external address bus. it becomes active (low) in synchronization with the falling edge of the clock in the t1 state of the bus cycle, and becomes inactive (high) in synchronization with the falling edge of the clock in the t3 state. it goes high in the idle state (ti). (vi) st0, st1 (status0, 1) ... output these are status signals which indicate the access type of the current bus cycle when external memory is referenced. the status changes in synchronization with the rising edge of the clock in the t1 and ti states of the bus cycle. st1 st0 bus cycle status 0 0 idle cycle 0 1 instruction fetch (branch) 1 0 operand data access 1 1 instruction fetch (continuous) in the following cases, the instruction fetch (branch) is output in the first bus cycle branched (t1 to t3 states). ? instruction fetch of the branched destination by the branch instructions (jmp, jr, jarl, bcond) ? instruction fetch of the source by the reti instruction ? instruction fetch of the jumped destination (interrupt/exception table) by reset, trap instruction, and interrupt instruction fetches other than the above output the status of the instruction fetch (continuous).
21 chapter 2 pin functions (9) p100 to p103 (port 10) ... 3-state i/o port 10 is a 4-bit i/o port that can be set in the input or output mode in 1-bit units. in addition to the function as a port, the pins constituting port 10 are used to input/output control signals, in the control mode, when an external bus master or asic is connected. if port 10 is accessed in 8-bit units, the higher 4 bits are ignored if the access is write, and undefined if the access is read. p102 and p103 function only as i/o pins and are not multiplexed with control pins. (a) port mode p100 to p103 can be set in the input or output mode, in 1-bit units, by port mode register (pm10). (b) control mode p100 and p101 function as input and output pins for bus hold control signals when the function is enabled by mode control register 10 (pmc10). (i) hldak (hold acknowledge) ... output this is an acknowledge signal that indicates that the v852 has set the address bus, data bus, and control bus in the high-impedance state in response to a bus hold request. as long as this signal is active, the address/data bus, and control signals remain in a high-impedance state. (ii) hldrq (hold request) ... input this input signal is used by an external device to request that the v852 relinquish control of the address, data bus, and control signals. this signal can be activated asynchronously with clkout. when this signal becomes active, the v852 sets the address/data bus and control signals in the high- impedance state, after the current bus cycle completes. if there is no current bus activity, the address/ data bus and control signals are immediately set to high-impedance. hldak is then made active and the bus and control lines are released. (10) clkout (clock output) ... output this pin outputs the system clock, even during reset. the output of this pin can be fixed to low level when the clock output inhibit mode is set by the psc register. (11) cksel (clock select) ... input this pin specifies the operation mode of the clock generation circuit. once set, the input value of this pin cannot be changed during operation. cksel operation mode 0 pll mode 1 direct mode (12) pllsel (pll select) ... input this input pin selects whether the system clock has a frequency one (1 f xx ) or five (5 f xx ) times the frequency (f xx ) of the external oscillator or external clock in the pll mode (cksel = 0). once set, the input value of this pin cannot be changed during operations. this pin has no function in the direct mode (cksel = 1). leave it as an unused pin.
22 chapter 2 pin functions pllsel f 0f xx 15 f xx (13) wait (wait) ... input this control signal input pin inserts a data wait state to the bus cycle, and can be activated asynchronously to clkout. this pin is sampled at the falling edge of the clock in the t2 and tw states of the bus cycle. if the set/hold time for the sampling timing is not satisfied, the wait state may not be inserted. (14) mode0, mode1 (mode0, 1) ... input these pins specify the operation mode of the v852. three operation modes can be selectable: single-chip mode, rom-less mode, and prom programming mode. the input value of these pins cannot be changed during normal operation. mode1 mode0 operation mode 0 0 rom-less mode 0 1 rfu (reserved) 1 0 single-chip mode 1 1 prom mode v pp = 5 v : read mode v pp = 12.5 v : programming mode (15) reset (reset) ... input the reset signal is an asynchronous input signal. a valid low-level signal on the reset pin initiates a system reset, regardless of the clock operation. in addition to normal system initialization/start functions, the reset signal is also used for exiting processor power-save modes (halt, idle, or stop). (16) x1, x2 (crystal) ... input an oscillator for system clock generation is connected across these pins. an external clock source can also be referenced by connecting the external clock input to the x1 pin and leaving the x2 pin open. (17) cv dd (power supply for clock generator) this pin supplies positive power to the internal clock generator. (18) cv ss (ground for clock generator) this is the ground pin of the internal clock generator. (19) v dd (power supply) this pin supplies positive power. connect all the v dd pins to a positive power supply. (20) v ss (ground) this is a ground pin. connect all the v ss pins to ground. (21) ic0 (internally connected) this pin is internally connected and must be connected to v ss .
23 chapter 2 pin functions 2.3.2 prom programming mode ( m pd70p3002 only) (1) a0 to a16 ... input these pins constitute an address bus that selects an address of the internal prom (00000h to 167ffh). (2) d0 to d7 ... i/o these pins constitute a data bus through which the internal prom is written/read. (3) pgm ... input this pin inputs a program pulse and is activated when v pp = 12.5 v, ce = 0, and oe = 1. upon activation, the program on d0 to d7 is written to an internal prom cell selected by a0 to a16. (4) ce ... input this is a chip enable input pin. when this signal is active, the program in prom can be written/read. (5) oe ... input this is an output enable signal input pin and inputs a read strobe signal to the internal prom. when the signal is activated while ce = 0, the program (1 byte) of the internal prom cell selected by a0 to a16, will appear at the outputs, d0 to d7. (6) v pp ... input this pin inputs a program pulse. when this pin is activated while v pp = 12.5 v, ce = 0, and oe = 1, the program byte on d0 to d7 can be written to the internal prom cell selected by a0 to a16. (7) v dd positive power supply pin (8) v ss gnd pin
24 chapter 2 pin functions i/o circuit type 5 8 5 2 8 5 8 5 8 5 8 5 3 2 2 1 2 C C C pin p00/to10, p01/to11 p02/tclr1, p03/ti1, p04/intp10 to p07/intp13 p10 to p17 p20/nmi p21/intp00 to p24/intp03 p25/so2 p26/si2, p27/sck2 p30/so0 p31/si0, p32/sck0 p33/txd, p34/rxd, p35/so1 p36/si1, p37/sck1 p40/ad0 to p47/ad7 p50/ad8 to p57/ad15 p60/a16 to p67/a23 p90/lben p91/uben p92/r/w p93/dstb p94/astb p95/st0, p96/st1 p97 p100/hldak p101/hldrq p102 p103 clkout cksel pllsel wait mode0, mode1 reset ic0 cv dd cv ss recommended connection input status : individually connect to v dd or v ss via resistor output status : open directly connect to v ss input status : individually connect to v dd or v ss via resistor output status : open 2.4 i/o circuit type and connection of unused pins when connecting to v dd or v ss via a resistor, it is recommended to connect a resistor with a resistance of 1 to 10 k w . open C C directly connect to v dd C directly connect to v ss directly connect to v dd directly connect to v ss
25 chapter 2 pin functions v dd p-ch n-ch in in v dd p-ch n-ch out v dd p-ch n-ch in/out data output disable input enable v dd p-ch n-ch in/out data output disable type 1 type 2 type 3 schmitt trigger input with hysteresis characteristics type 5 type 8 2.5 pin i/o circuits
26 chapter 2 pin functions [memo]
27 chapter 3 cpu functions chapter 3 cpu functions the cpu of the v852 is based on a risc architecture and executes most instructions in one clock cycle by using a 5-stage pipeline. 3.1 features minimum instruction execution time: 40 ns (at 25 mhz) address space: 16 mb linear thirty-two 32-bit general registers internal 32-bit architecture five-stage pipeline control multiplication/division instructions saturated operation instructions single-cycle 32-bit shift instruction long/short instruction format internal memory ? rom/prom : 90 kb ? ram : 3 kb four types of bit manipulation instructions ? set ? clear ? not ? test
28 chapter 3 cpu functions 3.2 cpu register set the registers of the v852 can be classified into two categories: a general-purpose program register set and a dedicated system register set. all the registers are 32 bits wide. for more details, refer to v850 family user's manual architecture . program register set system register set 31 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 zero register reserved for address generation interrupt stack pointer stack pointer (sp) global pointer (gp) text pointer (tp) element pointer (ep) link pointer (lp) 31 pc program counter 31 eipc eipsw exception/interrupt pc exception/interrupt psw 00 31 fepc fepsw fatal error pc fatal error psw 0 31 ecr exception cause register 0 31 psw program status word 0 0
29 chapter 3 cpu functions 3.2.1 program register set the program register set includes general registers and a program counter. (1) general registers thirty-two general registers, r0 to r31, are available. any of these registers can be used as a data variable or address variable. however, r0 and r30 are implicitly used by instructions, and care must be exercised when using these registers. also, r1 to r5 and r31 are implicitly used by the assembler and c compiler. therefore, before using these registers, their contents must be saved so that they are not lost. the contents must be restored to the registers after the registers have been used. also, for the details of r1 to r5 and r31, refer to ca850 users manual . table 3-1. program registers name usage operation r0 zero register always holds 0 r1 assembler-reserved register used as a working register for creating 32-bit immediate r2 interrupt stack pointer stack pointer for interrupt handler r3 stack pointer used to generate stack frame when function is called r4 global pointer used to access global variable in data area r5 text pointer used as a register specifying the start of the text area note r6 to r29 C address/data variable registers r30 element pointer base pointer register when memory is accessed r31 link pointer used by compiler when calling function pc program counter holds instruction address during program execution note area to allocate the program code. (2) program counter this register holds the address of the instruction under execution. the lower 24 bits of this register are valid, and bits 31 to 24 are fixed to 0. if a carry occurs from bit 23 to 24, it is ignored. bit 0 is fixed to 0, and branching to an odd address cannot be performed. figure 3-1. program counter (pc) 31 fixed to 0 24 23 instruction address under execution 10 0 pc after reset 00000000h
30 chapter 3 cpu functions 3.2.2 system register set system registers control the status of the cpu and hold interrupt information. table 3-2. system register numbers to read/write these system registers, specify a system register number indicated by the system register load/store instruction (ldsr or stsr instruction). figure 3-2. interrupt source register (ecr) bit position bit name meaning 31 to 16 fecc fatal error cause code exception code of nmi (refer to table 5-1 interrupt list ) 15 to 0 eicc exception/interrupt cause code exception code of exception/interrupt (refer to table 5-1 interrupt list ) system register name usage operation these registers save the pc and psw when an exception or interrupt occurs. because only one set of these registers is available, their contents must be saved when multiple interrupts are enabled. the high 8 bits of the eipc and the high 24 bits of the eipsw are fixed to 0. these registers save pc and psw when nmi occurs. the high 8 bits of the fepc and the high 24 bits of the fepsw are fixed to 0. if exception, maskable interrupt, or nmi occurs, this register will contain information referencing the interrupt source. the high 16 bits of this register are called fecc, to which exception code of nmi is set. the low 16 bits are called eicc to which exception code of exception/ interrupt is set (refer to figure 3-2 ). program status word is a collection of flags that indicate program status (instruction execution result) and cpu status (refer to figure 3-3 ). no. eipc status saving registers during interrupt status saving registers for nmi interrupt source register program status word 0 1 4 5 fepc fepsw psw reserved eipsw 2 3 ecr 6 to 31 31 fecc 16 15 eicc 0 ecr after reset 00000000h
31 chapter 3 cpu functions figure 3-3. program status word (psw) bit position bit name function 31 to 8 rfu reserved field (fixed to 0) 7 np nmi pending indicates that nmi processing is in progress. this flag is set when nmi is accepted, and disables multiple interrupts. 6 ep exception pending indicates that exception processing is in progress. this flag is set when exception is generated and does not accept maskable interrupt request. 5 id interrupt disable indicates that accepting external interrupt request is disabled. 4 sat saturated math this flag is set if result of executing saturated operation instruction overflows (if overflow does not occur, value of previous operation is held). 3 cy carry this flag is set if carry or borrow occurs as result of operation (if carry or borrow does not occur, it is reset). 2 ov overflow this flag is set if overflow occurs during operation (if overflow does not occur, it is reset). 1 s sign this flag is set if result of operation is negative. it is reset if result is positive. 0 z zero this flag is set if result of operation is zero (if result is not zero, it is reset). 31 rfu 10 z psw 2 s 3 ov 4 cy 5 sat 6 id 7 ep 8 np after reset 00000020h
32 chapter 3 cpu functions 3.3 operation modes 3.3.1 operation modes the v852 has the following operations modes. these modes are selected by the mode0 and mode1 pins. (1) single-chip mode in single-chip mode, after the system has been released from the reset status, the pins related to the bus interface are set for i/o port mode, execution branches to the reset entry address of the internal rom/prom, and instruction processing is started. the external expansion mode can be set in which external devices can be connected to the external memory area by setting the memory expansion mode register (mm) using instructions (refer to 3.4.6 (1) external expansion mode register (mm) ). (2) rom-less mode after the system reset has been released from the reset status, the pins related to the bus interface are set for the control mode, execution branches to the external device (memory) reset entry addresses, and instruction processing is started. instruction fetch and data access from internal rom/prom are disabled. (3) prom programming mode this mode is provided only for the prom version. in prom programming mode, the appropriate pins function to provide a m pd27c1001a compatible interface. by using a prom programmer, the internal prom of the v852 can be programmed. (4) prom read mode this mode is provided only for the prom version. in prom read mode, the appropriate pins function to provide a m pd27c1001a compatible interface. by using a prom programmer, the internal prom of the v852 can be read.
33 chapter 3 cpu functions 3.3.2 specifying operation mode the operation mode of the v852 is specified by using the mode0 and mode1 pins. set these pins in the application system. do not change the setting of these pins during operation. if the setting is changed during operation, the functionality is not guaranteed. (1) in normal mode mode1 mode0 operation mode 0 0 rom-less mode 0 1 rfu (reserved) 1 0 single-chip mode 1 1 rfu (reserved) (2) in prom mode pin status v pp mode1 mode0 5 v 0 0 rfu (reserved) 01 10 1 1 prom mode (read mode) 12.5 v 1 1 prom mode (programming mode) operation mode
34 chapter 3 cpu functions 3.4 address space 3.4.1 cpu address space the cpu of the v852 is of 32-bit architecture and supports up to 4 gb of linear address space (data space) during operand addressing (data access). when referencing instruction addresses, a linear address space (program space) of up to 16 mb is supported. figure 3-4 shows the cpu address space. figure 3-4. cpu address space ffffffffh cpu address space program area (16 mb linear) data area (4 gb linear) 01000000h 00ffffffh 00000000h
35 chapter 3 cpu functions 3.4.2 image (virtual address space) the core cpu supports 4 gb of "virtual" addressing space, or 256 memory blocks, each containing 16-mb memory locations. in actuality, the same 16-mb block is accessed regardless of the values of bits 31 to 24 of the cpu address. figure 3-5 shows the image of the virtual addressing space. because the higher 8 bits of a 32-bit cpu address are ignored and the cpu address is only seen as a 24-bit external physical address, the physical location xx000000h is equally referenced by multiple address values 00000000h, 010000000h, 02000000h... through fe000000h, ff000000h. figure 3-5. image on address space ffffffffh ff000000h feffffffh image cpu address space image image image image fe000000h fdffffffh 02000000h 01ffffffh 01000000h 00ffffffh 00000000h physical address space peripheral i/o internal ram external memory internal rom/prom xxffffffh xx000000h
36 chapter 3 cpu functions 3.4.3 wrap-around of cpu address space (1) program space of the 32 bits of the pc (program counter), the higher 8 bits are set to 0, and only the lower 24 bits are valid. even if a carry or borrow occurs from bit 23 to 24 as a result of branch address calculation, the higher 8 bits ignore the carry or borrow and remain at 0. therefore, the lower-limit address of the program space, address 00000000h, and the upper-limit address 00ffffffh are contiguous addresses. the condition in which the lower-limit address and upper-limit address of the program space are contiguous is called wrap-around. caution no instruction can be fetched from the 4-kb area of 00fff000h to 00ffffffh because this area is defined as peripheral i/o area. therefore, do not execute any branch operation instructions in which the destination address will reside in any part of this area. (2) data space the result of operand address calculation that exceeds 32 bits is ignored. therefore, the lower-limit address of the program space, address 00000000h, and the upper-limit address ffffffffh are contiguous addresses, and the data space is wrapped around at the boundary of these addresses. 00fffffeh 00ffffffh 00000000h 00000001h program space (+) direction (? direction program space fffffffeh ffffffffh 00000000h 00000001h data space (+) direction (? direction data space
37 chapter 3 cpu functions 3.4.4 memory map the v852 reserves areas as shown below. each mode is specified by using the mode0 and mode1 pins (refer to 3.3 operation modes ). xxffffffh single-chip mode xx100000h xx0fffffh xx000000h 4 kb 1 mb xxffe000h xxffdfffh xxfff000h xxffefffh peripheral i/o area internal ram area internal rom/prom area (access prohibited) single-chip mode (external expansion mode) peripheral i/o area internal ram area internal rom/prom area external memory area rom-less mode peripheral i/o area internal ram area external memory area 4 kb 16 mb
38 chapter 3 cpu functions 3.4.5 area (1) internal rom/prom area a 1-mb area corresponding to addresses 000000h to 0fffffh is reserved for the internal rom/prom area. the v852 is provided with a 90-kb area of addresses 000000h to 0167ffh as a physical internal rom/prom. the 38-kb area of addresses 016800h to 01ffffh are fixed to 0. the image of 000000h to 01ffffh is seen in the rest of the area (020000h to 0fffffh) interrupt/exception table the v852 increases the interrupt response speed by assigning destination addresses corresponding to interrupts/exceptions. the collection of these destination addresses is called an interrupt/exception table, which is located in the internal rom/prom area. when an interrupt/exception request is granted, execution jumps to the corresponding destination address, and the program written at that memory address is executed. figure 3-6 shows the names of interrupts/exceptions, and the corresponding addresses. xx0fffffh image image image xx0e0000h xx0dffffh xx040000h xx03ffffh xx020000h xx01ffffh xx000000h physical internal rom/prom internal rom/prom 1ffffh 16800h 167ffh 00000h interrupt/exception table fixed to ?
39 chapter 3 cpu functions figure 3-6. interrupt/exception table in the rom-less mode, the internal rom/prom area is referenced as external memory area. to assure correct operation after reset, the destination address for the reset routine should be set to address 0 of the external memory. 00000170h 00000160h 00000150h 00000140h 00000130h 00000120h 00000110h 00000100h 000000f0h 000000e0h 000000d0h 000000c0h 000000b0h 000000a0h 00000090h 00000080h 00000060h 00000050h 00000040h 00000010h 00000000h internal rom/prom area 16 bytes intcsi2 intcsi1 intp03 intp02 intp01 intp00 intst0 intsr0 intser0 intcsi0 intcm4 intp13/intcc13 intp12/intcc12 intp11/intcc11 intp10/intcc10 intov1 trap1n (n = 0 to fh) trap0n (n = 0 to fh) nmi reset ilgop
40 chapter 3 cpu functions (2) internal ram area a 4-kb area corresponding to addresses ffe000h through ffefffh is reserved as an internal ram area. the v852 is provided with 3 kb of addresses ffe000h to ffebffh as a physical internal ram area, and the rest of the area (ffec00h to ffefffh) is fixed to 0. xxffefffh fixed to ? xxffec00h xxffebffh xxffe000h internal ram
41 chapter 3 cpu functions (3) peripheral i/o area a 4-kb area of addresses fff000h to ffffffh is reserved as a peripheral i/o area. the v852 is provided with a 1-kb area of addresses fff000h to fff3ffh as a physical peripheral i/o area, and the image of fff000h to fff3ffh can be seen on the rest of the area (fff400h to ffffffh). the peripheral i/o register assigned with functions such as on-chip peripheral hardware operation mode specifying function and state monitoring function are all memory-mapped to the peripheral i/o area. instruction fetches are not allowed in this area. cautions 1. the least significant bit of an address is not decoded. if an odd address (2n+1) in the peripheral i/o area is referenced, the register at the next lowest even address (2n) will be accessed. 2. the v852 does not have a peripheral i/o register than can be accessed in word units. if a register is accessed with a word operation, the effects will be limited to the halfword referenced by the instruction. 3. if a register that can be accessed in byte units is accessed in half-word units, the higher 8 bits become undefined, if the access is a read operation. if a write access is made, only the data in the lower 8 bits is written to the register. 4. addresses that are not defined as registers are reserved for future expansion. if these addresses are accessed, the operation is undefined and not guaranteed. xxffffffh image image image image xxfffc00h xxfffbffh xxfff800h xxfff7ffh xxfff400h xxfff3ffh xxfff000h physical peripheral i/o peripheral i/o 3ffh 000h
42 chapter 3 cpu functions (4) external memory area the v852 can use an area of up to xx100000h to xxffdfffh in the single-chip mode and an area of up to xx000000h to xxffdfffh in the rom-less mode, for external memory accesses. in the external memory area, 64 kb, 256 kb, 1 mb, 4 mb, or 16 mb of physical external memory can be allocated when the external expansion mode is specified. the same image as that of the physical external memory can be seen continuously on the external memory area, as shown in figures 3-7 through 3-9, when the memory is not fully expanded (to 16 mb). the internal ram area, peripheral i/o area, and internal rom/prom area in the single-chip mode are not subject to external memory access. figure 3-7. external memory area (when expanded to 64 kb, 256 kb, or 1 mb) note the image of the physical external memory can be seen continuously in the rom-less mode. xxffffffh xx000000h physical external memory xffffh x0000h peripheral i/o internal ram image image image internal rom/prom note xxffdfffh xx100000h external memory
43 chapter 3 cpu functions figure 3-8. external memory area (when expanded to 4 mb) note the image of the physical external memory can be seen continuously in the rom-less mode. xxffffffh xx000000h physical external memory 3fffffh 000000h peripheral i/o internal ram image image image internal rom/prom note xxffdfffh xx100000h external memory
44 chapter 3 cpu functions figure 3-9. external memory area (when fully expanded) note it becomes the external memory area in the rom-less mode. xxffffffh peripheral i/o xx100000h xx000000h xxffdfffh internal ram external memory internal rom/prom note
45 chapter 3 cpu functions 3.4.6 external expansion mode the v852 allows external devices to be connected to the external memory space by using the pins of ports 4 through 10. to connect an external device, the port pins must be set in the external expansion mode by using the mode0 and mode1 pins and memory expansion mode register (mm). the mode0 and mode1 pins specify the operation mode of the v852. when mode0 = 0 and mode1 = 0, the v852 is set in the rom-less mode; when mode0 = 0 and mode1 = 1, the single-chip mode is used. in rom-less mode, pins in the port4 to port6 and the p90 to p94 become the control mode after reset, thereby enabling the external memory. in single-chip mode, port/control mode alternate function pins are in the port mode, thereby disabling the external device. when using an external device (external expansion mode), set the mm register by programming. in addition, when using the bus hold fucntion, set the pmc10 register to control mode.
46 chapter 3 cpu functions (1) memory expansion mode register (mm) this register sets the mode of each pin of ports 4 through 9. in the external expansion mode, an external device can be connected to the external memory area of up to 16 mb. however, the external device cannot be connected to the internal ram area, peripheral i/o area, and internal rom/prom area in the single-chip mode (not accessible even if connected physically). the mm register can be read/written in 8- or 1-bit units. bits 7, 5, and 4 of this register are fixed to 1. bit position bit name function 3 mm3 memory expansion mode specifies operation mode of p95 and p96 of port 9. mm3 operation mode p95 p96 0 port mode port 1 external expansion mode st0 st1 2 to 0 mm2 to mm0 memory expansion mode specifies operation mode of ports 4, 5, 6, and 9 (p90 to p94). address port 9 mm2 mm1 mm0 port 4 port 5 port 6 space (p90 to p94) 0 0 0 C port mode 0 1 1 64-kb expansion 1 0 0 256-kb expansion 1 0 1 1-mb expansion 1 1 0 4-mb expansion 1 1 1 16-mb expansion others rfu (reserved) remark for the details of the operation of each port pin, refer to 2.3 pin function . a16 a17 a20 a21 a22 a23 lben, uben, r/w, dstb, astb ad0 to ad7 a18 a19 ad8 to ad15 address fffff04ch mm 7 1 at reset b7h (in rom-less mode) b0h (in single-chip mode) 6 0 5 1 4 1 3 mm3 2 mm2 1 mm1 0 mm0
47 chapter 3 cpu functions 3.4.7 recommended use of address space the architecture of the v852 requires that a register that serves as a pointer be secured for address generation when executing operand data access in a data space. the operand data access can be performed directly from an instruction for 32-kbyte addresses in the pointer register. but general-perpose registers used as pointer registers have a limit. by minimizing performance degradation due to address calculations when changing a pointer value, the number of usable general registers for handling variables is maximized, and the program size can be saved. to enhance the efficiency of using the pointer in connection with the memory map of the v852, the following points are recommended: (1) program space of the 32 bits of the pc (program counter), the higher 8 bits are fixed to 0, and only the lower 24 bits are valid. therefore, a contiguous 16-mb space, starting from address 00000000h, unconditionally corresponds to the memory map of the program space. (2) data space for the efficient use of resources to be performed through the wrap-around feature of the data space, the continuous 8-mb address spaces 00000000h to 007fffffh and ff800000h to ffffffffh of the 4-gb cpu are used as the data space. with the v852, 16-mb physical address space is seen as 256 images in the 4-gb cpu address space. the highest bit (bit 23) of this 24-bit address is assigned as address sign- extended to 32 bits. application of wrap-around for example, when r = r0 (zero register) is specified for the ld/st disp 16 [r] instruction, an addressing range of 00000000h 32 kb can be referenced with the sign-extended, 16-bit displacement value. by mapping the external memory in the 24-kb area in the figure, all resources including on-chip hardware can be accessed with one pointer. the zero register (r0) is a register set to 0 by the hardware, and eliminates the need for additional registers for the pointer. (r =) 00000000h fffff000h ffffe000h ffff8000h internal rom/prom area 32 kb peripheral i/o area 4 kb internal ram area 4 kb external memory area 24 kb 00007fffh
48 chapter 3 cpu functions figure 3-10. recommended memory map note this area cannot be used as a program area. remark the areas shown by arrows indicate the recommended area. xxffffffh program space 00800000h 007fffffh 00100000h 000fffffh 00016800h 000167ffh 00000000h xx100000h xx0fffffh xx016800h xx0167ffh xx000000h data space 00ffec00h 00ffebffh 00ffe000h 00ffdfffh xxfff354h xxfff353h xxfff000h xxffefffh ffffffffh fffff354h fffff353h fffff000h ffffefffh xxffec00h xxffebffh xxffe000h xxffdfffh ffffec00h ffffebffh ffffe000h ffffdfffh 16 mb 8 mb peripheral i/o internal ram external memory external memory internal rom/prom internal rom/prom internal ram peripheral i/o note peripheral i/o internal ram internal rom/prom xx800000h xx7fffffh ff800000h ff7fffffh 01000000h 00ffffffh 00fff000h 00ffefffh external memory external memory
49 chapter 3 cpu functions bit units for manipulation 00h 00h undefined 3.4.8 peripheral i/o registers 1 bit 8 bits 16 bits fffff000h port 0 p0 fffff002h port 1 p1 fffff004h port 2 p2 fffff006h port 3 p3 fffff008h port 4 p4 undefined fffff00ah port 5 p5 fffff00ch port 6 p6 fffff012h port 9 p9 fffff014h port 10 p10 fffff020h port 0 mode register pm0 fffff022h port 1 mode register pm1 fffff024h port 2 mode register pm2 fffff026h port 3 mode register pm3 fffff028h port 4 mode register pm4 ffh fffff02ah port 5 mode register pm5 fffff02ch port 6 mode register pm6 fffff032h port 9 mode register pm9 fffff034h port 10 mode register pm10 fffff040h port 0 mode control register pmc0 00h fffff044h port 2 mode control register pmc2 01h fffff046h port 3 mode control register pmc3 00h fffff04ch memory expansion mode register mm b0h/b7h fffff054h port 10 mode control register pmc10 00h fffff060h data wait control register dwc ffffh fffff062h bus cycle control register bcc aaaah fffff070h power save control register psc 00h fffff078h system status register sys 0000000xb fffff084h baud rate generator register 0 brg0 undefined fffff086h baud rate generator prescaler mode register 0 bprm0 fffff088h clocked serial interface mode register 0 csim0 fffff08ah serial i/o shift register 0 sio0 fffff094h baud rate generator register 1 brg1 fffff096h baud rate generator prescaler mode register 1 bprm1 fffff098h clocked serial interface mode register 1 csim1 fffff09ah serial i/o shift register 1 sio1 undefined fffff0a8h clocked serial interface mode register 2 csim2 00h fffff0aah serial i/o shift register 2 sio2 undefined fffff0c0h asynchronous serial interface mode register 00 asim00 80h address function register name symbol r/w after reset r/w
50 chapter 3 cpu functions bit units for manipulation 00h w undefined r/w 00h 00h 1 bit 8 bits 16 bits fffff0c2h asynchronous serial interface mode register 01 asim01 r/w fffff0c4h asynchronous serial interface status register 0 asis0 fffff0c8h receive buffer 0 (9 bits) rxb0 r fffff0cah receive buffer 0l (lower 8 bits) rxb0l fffff0cch transmit shift register 0 (9 bits) txs0 fffff0ceh transmit shift register 0l (lower 8 bits) txs0l fffff100h interrupt control register ovic1 fffff102h interrupt control register p1ic0 fffff104h interrupt control register p1ic1 fffff106h interrupt control register p1ic2 fffff108h interrupt control register p1ic3 fffff10ah interrupt control register cmic4 fffff10ch interrupt control register csic0 fffff10eh interrupt control register seic0 fffff110h interrupt control register sric0 fffff112h interrupt control register stic0 fffff114h interrupt control register p0ic0 fffff116h interrupt control register p0ic1 fffff118h interrupt control register p0ic2 fffff11ah interrupt control register p0ic3 fffff11ch interrupt control register csic1 fffff11eh interrupt control register csic2 fffff166h in-service priority register ispr r 00h fffff170h command register prcmd w undefined fffff180h external interrupt mode register 0 intm0 fffff182h external interrupt mode register 1 intm1 fffff184h external interrupt mode register 2 intm2 fffff230h timer overflow status register tovs r/w fffff240h timer unit mode register 1 tum1 0000h fffff242h timer control register 1 tmc1 fffff244h timer output control register 1 toc1 fffff250h timer 1 tm1 r 0000h fffff252h capture/compare register 10 cc10 fffff254h capture/compare register 11 cc11 fffff256h capture/compare register 12 cc12 r/w fffff258h capture/compare register 13 cc13 fffff342h timer control register 4 tmc4 00h fffff350h timer 4 tm4 r 0000h fffff352h compare register 4 cm4 r/w undefined undefined 47h address function register name symbol r/w after reset
51 chapter 4 bus control function chapter 4 bus control function the v852 is provided with an external bus interface function by which external memories such as rom and ram, and i/o can be connected. 4.1 features 16-bit data bus external devices connected through multiplexed i/o port pins wait function ? programmable wait function, capable of inserting up to 3 wait states per 2 blocks ? external wait control through wait input pin idle state insertion function bus mastership arbitration function bus hold function 4.2 bus control pins the following pins are used for interfacing to external devices: external bus interface function corresponding port (pins) address/data bus (ad0 to ad7) port 4 (p40 to p47) address/data bus (ad8 to ad15) port 5 (p50 to p57) address bus (a16 to a23) port 6 (p60 to p67) read/write control (lben, uben, r/w, dstb) port 9 (p90 to p93) address strobe (astb) port 9 (p94) external wait control (wait) wait bus cycle status (st0, st1) port 9 (p95 to p96) bus hold control (hldrq, hldak) port 10 (p100 to p101) the bus interface function of each pin is enabled by the memory expansion mode register (mm). in rom-less mode, the bus interface function of each pin is unconditionally enabled by the mode0 and mode1 inputs. for the details of specifying an operation mode of the external bus interface, refer to 3.4.6 (1) memory expansion mode register (mm) .
52 chapter 4 bus control function 4.3 bus access 4.3.1 number of access clocks the number of basic clocks necessary for accessing each resource is as follows: bus cycle type resource (bus width) internal rom internal ram peripheral i/o external memory (32 bits) (32 bits) (16 bits) (16 bits) instruction fetch 1 3 disabled 3 + n operand data access 3 1 3 + n 3 + n remarks 1. unit: clock/access 2. n: number of inserted wait clock 4.3.2 bus width the v852 carries out peripheral i/o access and external memory access in 8-, 16-, or 32-bit units. the following shows the operation for each access. (1) byte access (8 bits) byte access is divided into two types, the access to even address and the access to odd address. (2) halfword access (16 bits) in halfword access to external memory, data is dealt with as it is because the data bus is 16-bit fixed. 0 7 0 7 8 15 b y te data external data bus (a) access to even address 0 7 0 7 8 15 byte data external data bus (b) access to odd address 00 15 15 halfword data external data bus
53 chapter 4 bus control function (3) word access (32 bits) in word access to external memory, the lower halfword is accessed first and then the upper halfword is accessed. 4.4 memory block function the 16-mb memory space is divided into memory blocks of 1-mb units. the programmable wait function and bus cycle operation mode can be independently controlled for every two memory blocks. 0 15 0 15 16 31 word data external data bus first 0 15 0 15 16 31 word data external data bus second block 15 block 14 block 13 block 12 block 11 block 10 block 9 block 8 block 7 block 6 block 5 block 4 block 3 block 2 block 1 block 0 ffffffh f00000h efffffh e00000h dfffffh d00000h cfffffh c00000h bfffffh b00000h afffffh a00000h 9fffffh 900000h 8fffffh 800000h 7fffffh 700000h 6fffffh 600000h 5fffffh 500000h 4fffffh 400000h 3fffffh 300000h 2fffffh 200000h 1fffffh 100000h 0fffffh 000000h ffffffh peripheral i/o area fff000h ffefffh internal ram area ffe000h external memory area internal rom/prom area
54 chapter 4 bus control function 4.5 wait function 4.5.1 programmable wait function to facilitate interfacing with low-speed memories and i/o devices, up to 3 data wait states can be inserted in a bus cycle for two memory blocks. the number of wait states can be programmed by using data wait control register (dwc). immediately after the system has been reset, three data wait states are automatically programmed for all memory blocks. (1) data wait control register (dwc) this register can be read/written in 16-bit units. bit position bit name function 15 to 0 dwn1 data wait dwn0 specifies number of wait states to be inserted (n = 0 to 7) dwn1 dwn0 number of wait states to be inserted 00 0 01 1 10 2 11 3 n blocks into which wait states are inserted 0 blocks 0/1 1 blocks 2/3 2 blocks 4/5 3 blocks 6/7 4 blocks 8/9 5 blocks 10/11 6 blocks 12/13 7 blocks 14/15 cautions 1. block 0 is reserved for the internal rom/prom area in the single-chip mode. it is not subject to programmable wait control, regardless of the setting of dwc, and is always accessed without wait states. 2. the internal ram area of block 15 is not subject to programmable wait control and is always accessed without wait states. the peripheral i/o area of this block is not subject to programmable wait control, either. the only wait control is dependent upon the execution of each peripheral function. address fffff060h dwc 15 dw71 at reset ffffh 14 dw70 13 dw61 12 dw60 11 dw51 10 dw50 9 dw41 8 dw40 7 dw31 6 dw30 5 dw21 4 dw20 3 dw11 2 dw10 1 dw01 0 dw00
55 chapter 4 bus control function 4.5.2 external wait function when an extremely slow device, i/o, or asynchronous system is connected, any number of wait states can be inserted in a bus cycle by sampling the external wait pin (wait) to synchronize with the external device. the external wait signal does not affect the access times of the internal rom/prom, internal ram, and peripheral i/o areas. input of the external wait signal can be done asynchronously to clkout and is sampled at the falling edge of the clock in the t2 and tw states of a bus cycle. if the set-up and hold time of the wait input is not satisfied, the wait state may or may not be inserted in the next state. 4.5.3 relationships between programmable wait and external wait a wait cycle is inserted as a result of an or operation between the wait cycle specified by the set value of programmable wait and the wait cycle controlled by the wait pin. in other words, the number of wait cycles is determined by the programmable wait value or the length of evaluation at the wait input pin. for example, if the number of programmable wait states is 2 and the timing of the wait pin input signal is as illustrated below, three wait states will be inserted in the bus cycle. figure 4-1. example of inserting wait states remark : sampling timing wait by wait pin programmable wait wait control clkout t1 t2 tw tw tw t3 wait pin wait by wait pin programmable wait wait control
56 chapter 4 bus control function 4.6 idle state insertion function to facilitate interfacing with low-speed memory devices and meeting the data output float delay time (t df ) on memory read accesses, one idle state (ti) can be inserted into the current bus cycle after the t3 state. the bus cycle following continuous bus cycles starts after one idle state. specifying insertion of the idle state is programmable by using the bus cycle control register (bcc). immediately after the system has been reset, idle state insertion is automatically programmed for all memory blocks. (1) bus cycle control register (bcc) this register can be read/written in 16-bit units. bit position bit name function 15, 13, 11, bcn1 bus cycle 9, 7, 5, 3, 1 (n = 0 to 7) specifies insertion of idle state. 0: not inserted 1: inserted n blocks into which idle state is inserted 0 blocks 0/1 1 blocks 2/3 2 blocks 4/5 3 blocks 6/7 4 blocks 8/9 5 blocks 10/11 6 blocks 12/13 7 blocks 14/15 cautions 1. block 0 is reserved for the internal rom/prom area in the single-chip mode and therefore, no idle state is specified for this block. 2. the internal ram area and peripheral i/o area of block 15 are not subject to insertion of the idle state. 3. always set the bcc bits 0, 2, 4, 6, 8, 10, 12 and 14 to 0. normal operation is not guaranteed when they are set to 1. address fffff062h bcc 15 bc71 at reset aaaah 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 bc61 0 bc51 0 bc41 0 bc31 0 bc21 0 bc11 0 bc01 0
57 chapter 4 bus control function 4.7 bus hold function 4.7.1 outline of function when p100 and p101 of port 10 are programmed to be in the control mode, the functions of the hldrq and hldak pins become valid. when the hldrq pin becomes active (low) indicating that other bus master is requesting acquisition of the bus, the external address/data bus and strobe pins go into a high-impedance state, and the bus is released (bus hold status). when the hldrq pin becomes inactive (high) indicating that the request for the bus is cleared, these pins are driven again. v852 internal operation continues until external memory is accessed during bus hold. in the bus hold status, the hldak pin becomes active (low). this feature can be used to design a system where two or more bus masters exist, such as when a multi-processor configuration is used and when a dma controller is connected. however, bus hold requests are accepted neither between the first and the second word access, nor between read access and write access during read modify write access of bit manipulation instructions. 4.7.2 bus hold procedure the procedure of bus hold function is illustrated below. <1> hldrq = 0 accepted <2> all bus cycle start request pending <3> end of current bus cycle <4> bus idle status <5> hldak = 0 <6> hldrq = 1 accepted <7> hldak = 1 <8> clears bus cycle start request pending <9> start of bus cycle 4.7.3 operation in power save mode in the stop or idle mode, the system clock is stopped. consequently, the bus hold status is not set even if the hldrq pin becomes active. in the halt mode, the hldak pin immediately becomes active when the hldrq pin becomes active, and the bus hold status is set. when the hldrq pin becomes inactive, the hldak pin becomes inactive. as a result, the bus hold status is cleared, and the halt mode is set again. - - - - - - - - - - - - - - - - - - - - - - normal status bus hold status normal status hldrq hldak <1><2> <3> <4> <5> <6><7> <8><9>
58 chapter 4 bus control function 4.8 bus timing (1) memory read (0 wait) remarks 1. indicates the sampling timing when the number of programmable waits is set to 0. 2. the dotted line indicates the high-impedance state. clkout a16 to a23 ad0 to ad15 astb r/w dstb wait st0, st1 t1 t2 t3 address address uben lben data
59 chapter 4 bus control function (2) memory read (1 wait) remarks 1. indicates the sampling timing when the number of programmable waits is set to 0. 2. the dotted line indicates the high-impedance state. clkout a16 to a23 ad0 to ad15 astb r/w dstb wait st0, st1 t1 t2 tw address address uben lben data t3
60 chapter 4 bus control function (3) memory read (0 wait, idle state) remarks 1. indicates the sampling timing when the number of programmable waits is set to 0. 2. the dotted line indicates the high-impedance state. clkout a16 to a23 ad0 to ad15 astb r/w dstb wait st0, st1 t1 t2 t3 address address uben lben data ti
61 chapter 4 bus control function (4) memory read (1 wait, idle state) remarks 1. indicates the sampling timing when the number of programmable waits is set to 0. 2. the dotted line indicates the high-impedance state. clkout a16 to a23 ad0 to ad15 astb r/w dstb wait st0, st1 t1 t2 tw address address uben lben data t3 ti
62 chapter 4 bus control function (5) memory write (0 wait) note ad0 to ad7 output invalid data when odd address byte data is accessed. ad8 to ad15 output invalid data when even address byte data is accessed. remarks 1. indicates the sampling timing when the number of programmable waits is set to 0. 2. the dotted line indicates the high-impedance state. clkout a16 to a23 ad0 to ad15 astb r/w dstb wait st0, st1 t1 t2 t3 address address uben lben data note
63 chapter 4 bus control function (6) memory write (1 wait) note ad0 to ad7 output invalid data when odd address byte data is accessed. ad8 to ad15 output invalid data when even address byte data is accessed. remarks 1. indicates the sampling timing when the number of programmable waits is set to 0. 2. the dotted line indicates the high-impedance state. clkout a16 to a23 ad0 to ad15 astb r/w dstb wait st0, st1 t1 t2 tw address address uben lben data t3 note
64 chapter 4 bus control function (7) bus hold timing remarks 1. indicates the sampling timing. 2. the dotted line indicates the high-impedance state. caution in case of transition to the bus hold status after a write cycle, a momentary high-level output from the r/w pin may occur just before the hldak signal changes from high-level to low-level. clkout hldrq hldak t2 address uben lben a16 to a23 ad0 to ad15 astb r/w dstb t3 th th th th ti t1 address address data address undefined wait st0, st1 undefined
65 chapter 4 bus control function 4.9 bus priority there are four external bus cycles: bus hold, operand data access, instruction fetch (branch), and instruction fetch (continuous). the bus hold cycle is given the highest priority, followed by operand data access, instruction fetch (branch), and instruction fetch (continuous), in that order. the instruction fetch cycle may be inserted in between the read access and write access of read-modify-write access. the instruction fetch cycle and bus hold cycle are not inserted between the lower half-word access and higher half-word access of word operations. table 4-1. bus priority external bus cycle priority bus hold 1 operand data access 2 instruction fetch (branch) 3 instruction fetch (continuous) 4 4.10 memory boundary operation condition 4.10.1 program space (1) do not execute branch to the peripheral i/o area or continuous fetch from the internal ram area to the peripheral i/o area. when executing the branch or continuous fetch, it is impossible to fetch from external memory. if it is executed nevertheless, the nop instruction code is continuously fetched. (2) a prefetch operation straddling over the peripheral i/o area (invalid fetch) does not take place if a branch instruction exists at the upper-limit address of the internal ram area. 4.10.2 data space only the address aligned at the half-word (when the least significant bit of the address is 0)/word (when the lowest 2 bits of the address are 0) boundary is accessed for data half-word (16 bits)/word (32 bits) long. therefore, access that straddles over the memory or memory block boundary does not take place. the word access to the external memory is performed in the order of the lower half-word and then the higher half- word. refer to v850 family user's manual architecture for details.
66 chapter 4 bus control function 4.11 internal peripheral i/o interface access to the internal peripheral i/o area is not output to the external bus. therefore, the internal peripheral i/o area can be accessed in parallel with instruction fetch access. accesses to the internal peripheral i/o area takes, in most cases, three clock cycles. however, accesses to the following timer/counter registers may take from 3 to 4 cycles. peripheral i/o register access tm1 read tm4 cc10 read/write cc11 cc12 cc13 cm4 write
67 chapter 5 interrupt/exception processing function chapter 5 interrupt/exception processing function the v852 is provided with a dedicated interrupt controller (intc) for interrupt processing and can process a total of 17 interrupt requests. an interrupt is an event that occurs independently of program execution, and an exception is an event that occurs dependently on program execution. generally, an exception takes precedence over an interrupt. the v852 can process interrupt requests from the internal peripheral hardware and external sources. moreover, exception processing can be started (exception trap) by a trap instruction (software exception) or by generation of an exception event (fetching of an illegal op code). 5.1 features interrupt ? non-maskable interrupt: 1 source ? maskable interrupt: 16 sources ? 8 levels programmable priorities ? multiple interrupt control according to priority ? each maskable interrupt can be individually disabled. ? noise elimination, edge detection, and rising and/or falling edge of external interrupt request signal can be specified. exception ? software exception: 32 sources ? exception trap: 1 source (illegal op code exception) these interrupt/exception sources are listed in table 5-1.
68 chapter 5 interrupt/exception processing function table 5-1. interrupt list reset interrupt reset C reset input C C 0000h 00000000h undefined non-maskable interrupt nmi C nmi input C C 0010h 00000010h nextpc exception trap0n note C trap instruction C C 004n note h 00000040h nextpc exception trap1n note C trap instruction C C 005n note h 00000050h nextpc exception trap exception ilgop C illegal op code C C 0060h 00000060h nextpc maskable interrupt intov1 ovic1 timer 1 overflow rpu 0 0080h 00000080h nextpc interrupt intp10/intcc10 p1ic0 intp10 pin/cc10 pin/rpu 1 0090h 00000090h nextpc coincidence interrupt intp11/intcc11 p1ic1 intp11 pin/cc11 pin/rpu 2 00a0h 000000a0h nextpc coincidence interrupt intp12/intcc12 p1ic2 intp12 pin/cc12 pin/rpu 3 00b0h 000000b0h nextpc coincidence interrupt intp13/intcc13 p1ic3 intp13 pin/cc13 pin/rpu 4 00c0h 000000c0h nextpc coincidence interrupt intcm4 cmic4 cm4 coincidence rpu 5 00d0h 000000d0h nextpc interrupt intcsi0 csic0 csi0 transmission/ sio 6 00e0h 000000e0h nextpc reception completion interrupt intser0 seic0 uart0 reception error sio 7 00f0h 000000f0h nextpc interrupt intsr0 sric0 uart0 reception sio 8 0100h 00000100h nextpc completion interrupt intst0 stic0 uart0 transmission sio 9 0110h 00000110h nextpc completion interrupt intp00 p0ic0 intp00 pin pin 10 0120h 00000120h nextpc interrupt intp01 p0ic1 intp01 pin pin 11 0130h 00000130h nextpc interrupt intp02 p0ic2 intp02 pin pin 12 0140h 00000140h nextpc interrupt intp03 p0ic3 intp03 pin pin 13 0150h 00000150h nextpc interrupt intcsi1 csic1 csi1 transmission/ sio 14 0160h 00000160h nextpc reception completion interrupt intcsi2 csic2 csi2 transmission/ sio 15 0170h 00000170h nextpc reception completion note n: value of 0 to fh remarks 1. default priority: priority that takes precedence when two or more maskable interrupt requests of the same priority level occur at the same time. the highest priority is 0. restored pc: the value of the pc saved to eipc or fepc when interrupt/exception processing is started. however, the value of the pc saved when an interrupt is granted during the divh (division) instruction execution is the value of the pc of the current instruction (divh). 2. the execution address of the illegal instruction when an illegal op code exception occurs is calculated as follows: (restored pcC4) interrupt/exception source control register generating source type classifi- cation name generating unit default priority vector address restored pc exception code software exception
69 chapter 5 interrupt/exception processing function 5.2 non-maskable interrupt the non-maskable interrupt request is accepted unconditionally, even when interrupts are disabled (di states) in the interrupt disabled (di) status. the nmi is not subject to priority control and takes precedence over all the other interrupts. the non-maskable interrupt request is input from the nmi pin. when the valid edge specified by the bit 0 (esn0) of the external interrupt mode register 0 (intm0) is detected on the nmi pin, the interrupt occurs. while the service routine of the non-maskable interrupt is being executed, (psw.np = 1), the acceptance of another non-maskable interrupt request is kept pending. the pending nmi is accepted after the original service routine of the non-maskable interrupt under execution has been terminated (by the reti instruction), or when psw.np is cleared to 0 by the ldsr instruction. note that if two or more nmi requests are input during the execution of the service routine for an nmi, the number of nmis that will be acknowledged after psw.np goes to 0, is only one.
70 chapter 5 interrupt/exception processing function 5.2.1 accepting operation if the non-maskable interrupt is generated by nmi input, the cpu performs the following processing, and transfers control to the handler routine: (1) saves the contents of restored pc to fepc. (2) saves the current psw to fepsw. (3) writes exception code 0010h to the higher half-word (fecc) of ecr. (4) sets the np and id bits of psw and clears the ep bit. (5) loads the vector address (00000010h) of the non-maskable interrupt routine to the pc, and transfers control. figure 5-1 illustrates how the non-maskable interrupt is processed. figure 5-1. non-maskable interrupt processing nmi input non-maskable interrupt request interrupt processing interrupt request pending fepc fepsw ecr. fecc psw. np psw. ep psw. id pc <- restored pc <- psw <- 0010h <- 1 <- 0 <- 1 <- 00000010h intc accepted cpu processing psw. np 1 0
71 chapter 5 interrupt/exception processing function figure 5-2. accepting non-maskable interrupt request (a) if a new nmi request is generated while an nmi service routine is executing: (b) if a new nmi request is generated twice while an nmi service routine is executing: main routine nmi request -> nmi request -> (psw. np = 1) nmi request pending because psw. np = 1 pending nmi request processed main routine nmi request -> nmi request -> kept pending because nmi service program is being processed kept pending because nmi service program is being processed nmi request -> only one nmi request is accepted even though two or more nmi requests are generated
72 chapter 5 interrupt/exception processing function 5.2.2 restore operation execution is restored from the non-maskable interrupt processing by the reti instruction. operation of reti instruction when the reti instruction is executed, the cpu performs the following processing, and transfers control to the address of the restored pc. (1) restores the values of pc and psw from fepc and fepsw, respectively, because the ep bit of psw is 0 and the np bit of psw is 1. (2) transfers control back to the address of the restored pc and psw. figure 5-3 illustrates how the reti instruction is processed. figure 5-3. reti instruction processing caution when the psw.ep bit and psw.np bit have been changed using the ldsr instruction during the non-maskable interrupt processing, to restore the values of pc and psw when normal execution returns via the reti instruction, it is necessary to set psw.ep = 0 and psw.np = 1 immediately before the reti instruction is executed using the ldsr instruction. remark the solid lines indicate the cpu processing. reti instruction original processing restored pc psw <- eipc <- eipsw psw. ep 1 0 1 0 pc psw <- fepc <- fepsw psw. np
73 chapter 5 interrupt/exception processing function 5.2.3 np flag the np flag is a status flag that indicates that non-maskable interrupt (nmi) processing is under execution. this flag is set when the nmi interrupt has been accepted, and masks the all interrupt requests to prohibit multiple interrupts from being acknowledged. bit position bit name function 7 np nmi pending indicates that nmi interrupt processing is under execution 0: no nmi interrupt processing 1: nmi interrupt currently processing 5.2.4 noise elimination for nmi pin noise is eliminated from the nmi pin by analog delay. the delay time is 60 to 220 ns. input of a signal whose level changes within a time interval shorter than this delay time is not accepted internally. the nmi pin is used for releasing the software stop mode. since the internal system clock stops in the software stop mode, noise elimination using the system clock is not performed. 5.2.5 external interrupt mode register 0 (intm0) intm0 is a register that specifies the valid edge of the non-maskable interrupt (nmi). the valid edge of nmi can be specified as the rising or falling edge by the esn0 bit of this register. this register can be read or written in 8- or 1- bit units. bit position bit name function 0 esn0 edge select nmi specifies valid edge of nmi pin 0: falling edge 1: rising edge address fffff180h intm0 7 0 at reset 00h 6 0 5 0 4 0 3 0 2 0 1 0 0 esn0 31 10 z psw 2 s 3 ov 4 cy 5 sat 6 id 7 ep 8 np at reset 00000020h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
74 chapter 5 interrupt/exception processing function 5.3 maskable interrupts maskable interrupt requests can be masked by interrupt control registers. the v852 has 16 maskable interrupt sources. if two or more maskable interrupt requests are generated at the same time, they are accepted according to the default priority. in addition to the default priority, eight levels of priorities can be specified by using the interrupt cont rol registers, allowing programmable priority control. when an interrupt request has been acknowledged, the interrupt disabled (di) status is set and the acceptance of other maskable interrupts is disabled. when the ei instruction is executed in an interrupt processing routine, the interrupt enabled (ei) status is set which enables interrupts having a higher priority to immediately interrupt the current service routine in progress. note that only interrupts with a higher priority will have this capability; interrupts with the same priority level cannot be nested. to perform multiple interrupts, the next preprocessings are necessary. <1> save eipc and eipsw to memory or general-perpose register before executing the ei instruction <2> execute the di instruction before executing the reti instruction, and return the value that saved in the process of <1> to the eipc and eipsw
75 chapter 5 interrupt/exception processing function 5.3.1 block diagram figure 5-4. maskable interrupt block diagram xx: identification name of each peripheral unit (ov, p1, cm, cs, se, sr, st, p0) n: peripheral unit number (0 to 4) 5.3.2 operation if a maskable interrupt occurs, the cpu performs the following processing, and transfers control to a vector routine: (1) saves the value of pc to eipc. (2) saves the current psw to eipsw. (3) writes an exception code to the lower half-word of ecr (eicc). (4) sets the id bit of psw and clears the ep bit. (5) loads the corresponding vector address to the pc, and transfers control. figure 5-5 illustrates how the maskable interrupts are processed. ovif1 p1if0 p1if1 p1if2 p1if3 cmif4 csif0 seif0 srif0 stif0 p0if0 p0if1 p0if2 p0if3 csif1 csif2 intp00 intp01 intp02 intp03 intm1 edge detection 0 1 2 3 0 intm2 intp10 intp11 intp12 intp13 edge detection intcsi0 intser0 intsr0 intst0 1 2 3 0 1 2 3 selector rpu sio intov1 intp10/intcc10 intp11/intcc11 intp12/intcc12 intp13/intcc13 intcm4 internal bus xxmkn (interrupt mask flag) ispr cpu psw id vector address generation circuit 0 7 priority controller xxprn interrupt request interrupt request acknowledge halt mode release signal intcsi1 intcsi2
76 chapter 5 interrupt/exception processing function figure 5-5. maskable interrupt processing the int input masked by the interrupt control registers and that occurs while a previous interrupt is being processed (when psw.np = 1 or psw.id = 1) are internally monitored by the interrupt controller. when the interrupts are unmasked, or when psw.np = 0 and psw.id = 0 by using the reti and ldsr instructions, the new maskable interrupts can then be acknowledged, by the pending int input, and processed. maskable interrupt request interrupt processing eipc eipsw ecr. eicc psw. ep psw. id pc <- <- <- <- <- <- intc accepted cpu processing xxif = 1 no yes xxmk = 0 priority higher than that of interrupt currently processed? interrupt request pending psw. np psw. id interrupt process pending no no no no 1 0 1 0 interrupt request? int input yes yes yes yes priority higher than that of other interrupt request? highest default priority of interrupt requests with same priotity? interrupt unmasked? restored pc psw exception code 0 1 vector address
77 chapter 5 interrupt/exception processing function 5.3.3 restore to restore or return execution from the maskable interrupt service routine, the reti instruction is used. operation of reti instruction when the reti instruction is executed, the cpu performs the following steps, and transfers control to the address of the restored pc. (1) restores the values of pc and psw from eipc and eipsw because the ep bit of psw is 0 and the np bit of psw is 0. (2) transfers control to the address of the restored pc and psw. figure 5-6 illustrates the processing of the reti instruction. figure 5-6. reti instruction processing caution when the psw.ep bit and psw.np bit have been changed using the ldsr instruction during the maskable interrupt processing, to restore the values of pc and psw when normal execution returns via the reti instruction, it is necessary to return each value of psw.ep and psw.np to 0 immediately before the reti instruction is executed using the ldsr instruction. remark the solid lines indicate the cpu processing. reti instruction restores original processing pc psw <- eipc <- eipsw psw. ep 1 0 1 0 pc psw <- fepc <- fepsw psw. np
78 chapter 5 interrupt/exception processing function 5.3.4 priorities of maskable interrupts the v852 processes multiple interrupts which accept another interrupt during interrupt processing. multiple interrupts can be controlled by the priority level. there are two priority control criteria in the v852: control based on the default priority levels, and programmable priority control based on interrupt priority specification bit (xxprn). the priority level control by the default priority levels performs interrupt processing according to the priority level (default priority level) preassigned to each interrupt request when several interrupts of the same priority by xxprn occur at the same time (refer to table 5-1. list of interrupts ). the programmable priority level control customizes the interrupt requests into eight levels according to the setting of the priority level specification flag. note that when an interrupt is acknowledged, the id flag of psw is automatically set to 1. therefore, when multiple interrupts are to be used, clear the id flag to 0 beforehand (for example, by placing the ei instruction into the interrupt service program) to set the interrupt enable mode.
79 chapter 5 interrupt/exception processing function figure 5-7. example of interrupt nesting process (1/2) remarks 1. a to u in the figure are the names of interrupt requests shown for the sake of explanation. 2. the default priority in the figure indicates the relative priority between two interrupt requests. caution the values of eipc and eipsw must be saved before executing multiple interrupts. main routine interrupt request c -> (level 3) processing of c ei ei interrupt request a -> (level 3) interrupt request b (level 2) -> interrupt request e -> (level 2) interrupt request g -> (level 1) interrupt request d (level 2) -> interrupt request f (level 3) -> interrupt request h (level 1) -> processing of a processing of d processing of e processing of f processing of g processing of h processing of b interrupt request b is accepted because the priority of b is higher than that of a and interrupts are enabled. although the priority of interrupt request d is higher than that of c, d is kept pending because interrupts are disabled. interrupt request f is kept pending even if interrupts are enabled because its priority is lower than that of e. interrupt request h is kept pending even if interrupts are enabled because its priority is the same as that of g. ei ei
80 chapter 5 interrupt/exception processing function figure 5-7. example of interrupt nesting process (2/2) notes 1. lower default priority 2. higher default priority main routine interrupt request l -> (level 2) processing of j ei interrupt request i -> (level 2) interrupt request j (level 3) -> interrupt request o -> (level 3) interrupt request s -> (level 1) interrupt request p (level 2) -> processing of i processing of l processing of n processing of m processing of s processing of k interrupt request j is kept pending because its priority is lower than that of i. k that occurs after j is accepted because it has the higher priority. interrupt requests m and n are kept pending because processing of l is performed in the interrupt disabled status. pending interrupt requests are accepted after processing of interrupt request l. at this time, interrupt requests n is accepted first even though m has occurred first because the priority of n is higher than that of m. if levels 3 to 0 are accepted ei ei ei ei ei interrupt request k (level 1) -> processing of o processing of p processing of q processing of r interrupt request n (level 1) -> interrupt request q (level 1) -> interrupt request r (level 0) -> interrupt request t (level 2) -> interrupt request u (level 2) -> processing of u processing of t pending interrupt requests t and u are accepted after processing of s. because the priorities of t and u are the same, u is accepted first according to the default priority, regardless of the order in which the interrupt requests have been generated. note 1 note 2 interrupt request m (level 3) ->
81 chapter 5 interrupt/exception processing function figure 5-8. example of processing interrupt requests simultaneously generated main routine interrupt request a (level 2) interrupt request b (level 1) interrupt request c (level 1) processing of interrupt request b processing of interrupt request c ? interrupt requests b and c are accepted first according to their priorities. ? because the priorities of b and c are the same, b is accepted first because it has the higher default priority. ei default priority a>b>c processing of interrupt request a
82 chapter 5 interrupt/exception processing function address fffff100h to fffff11eh xxicn 7 xxifn at reset 47h 6 xxmkn 5 0 4 0 3 0 2 xxprn2 1 xxprn1 0 xxprn0 5.3.5 interrupt control register (xxicn) an interrupt control register is assigned to each maskable interrupt and holds the control conditions for each maskable interrupt request. the interrupt control register can be read/written in 8- or 1-bit units. bit position bit name function 7 xxifn interrupt request flag interrupt request flag 0: interrupt request not issued 1: interrupt request issued xxifn flag is automatically reset by hardware when interrupt request is accepted. 6 xxmkn mask flag interrupt mask flag 0: enables interrupt processing 1: disables interrupt processing (pending) 2 to 0 xxprn2 to xxprn0 priority specifies eight levels of priorities for each interrupt xxprn2 xxprn1 xxprn0 interrupt priority specification bit 0 0 0 specifies level 0 (highest) 0 0 1 specifies level 1 0 1 0 specifies level 2 0 1 1 specifies level 3 1 0 0 specifies level 4 1 0 1 specifies level 5 1 1 0 specifies level 6 1 1 1 specifies level 7 (lowest) remark xx: identification name of each peripheral unit (ov, p1, cm, cs, se, sr, st, p0) n: peripheral unit number (0 to 4)
83 chapter 5 interrupt/exception processing function the address and bit of each interrupt control register is as follows. table 5-2. addresses and bits of interrupt control register address register bit 76543210 fffff100h ovic1 ovif1 ovmk1 0 0 0 ovpr12 ovpr11 ovpr10 fffff102h p1ic0 p1if0 p1mk0 0 0 0 p1pr02 p1pr01 p1pr00 fffff104h p1ic1 p1if1 p1mk1 0 0 0 p1pr12 p1pr11 p1pr10 fffff106h p1ic2 p1if2 p1mk2 0 0 0 p1pr22 p1pr21 p1pr20 fffff108h p1ic3 p1if3 p1mk3 0 0 0 p1pr32 p1pr31 p1pr30 fffff10ah cmic4 cmif4 cmmk4 0 0 0 cmpr42 cmpr41 cmpr40 fffff10ch csic0 csif0 csmk0 0 0 0 cspr02 cspr01 cspr00 fffff10eh seic0 seif0 semk0 0 0 0 sepr02 sepr01 sepr00 fffff110h sric0 srif0 srmk0 0 0 0 srpr02 srpr01 srpr00 fffff112h stic0 stif0 stmk0 0 0 0 stpr02 stpr01 stpr00 fffff114h p0ic0 p0if0 p0mk0 0 0 0 p0pr02 p0pr01 p0pr00 fffff116h p0ic1 p0if1 p0mk1 0 0 0 p0pr12 p0pr11 p0pr10 fffff118h p0ic2 p0if2 p0mk2 0 0 0 p0pr22 p0pr21 p0pr20 fffff11ah p0ic3 p0if3 p0mk3 0 0 0 p0pr32 p0pr31 p0pr30 fffff11ch csic1 csif1 csmk1 0 0 0 cspr12 cspr11 cspr10 fffff11eh csic2 csif2 csmk2 0 0 0 cspr22 cspr21 cspr20
84 chapter 5 interrupt/exception processing function 5.3.6 external interrupt mode registers 1 and 2 (intm1 and intm2) these registers specify the valid edges of external interrupt requests intp00 to intp03 and intp10 to intp13 that are input from external pins. intm1 controls intp00 to intp03, and intm2 controls intp10 to intp13. the valid edge of each pin can be specified to be the rising, falling, and both rising and falling edges. both the registers can be read/written in 8- or 1-bit units. bit position bit name function 7, 5, 3, 1 es0n1 edge select 6, 4, 2, 0 es0n0 specifies valid edge of intp0n pin (n = 3 to 0) es0n1 es0n0 operation 0 0 falling edge 0 1 rising edge 1 0 rfu (reserved) 1 1 both rising and falling edges bit position bit name function 7, 5, 3, 1 es1n1 edge select 6, 4, 2, 0 es1n0 specifies valid edge of intp1n pin (n = 3 to 0) es1n1 es1n0 operation 0 0 falling edge 0 1 rising edge 1 0 rfu (reserved) 1 1 both rising and falling edges address fffff182h intm1 control pin 7 es031 intp03 intp02 intp01 intp00 control pin intp13 intp12 intp11 intp10 at reset 00h 6 es030 5 es021 4 es020 3 es011 2 es010 1 es001 0 es000 address fffff184h intm2 7 es131 at reset 00h 6 es130 5 es121 4 es120 3 es111 2 es110 1 es101 0 es100
85 chapter 5 interrupt/exception processing function 5.3.7 in-service priority register (ispr) this register holds the priority level of the maskable interrupt currently accepted. when an interrupt request is accepted, the bit of this register corresponding to the priority level of that interrupt is set to 1 and remains set while the interrupt is serviced. when the reti instruction is executed, the bit corresponding to the interrupt request having the highest priority is automatically reset to 0 by hardware. however, it is not reset when execution is returned from non-maskable processing or exception processing. this register can be only read in 8- or 1- bit units. bit position bit name function 7 to 0 ispr7 to ispr0 in-service priority flag indicates priority of interrupt currently accepted 0: interrupt request with priority n not accepted 1: interrupt request with priority n accepted remark n: 0 to 7 (priority level) 5.3.8 maskable interrupt status flag the interrupt disable status flag (id) of the psw controls the enabling and disabling of maskable interrupt requests. as a status flag, it also displays the current maskable interrupt acceptance condition. bit position bit name function 5 id interrupt disable indicates enabling or disabling maskable interrupt processing. 0: maskable interrupt accepting enabled 1: maskable interrupt accepting disabled (pending) it is set to 1 by the di instruction and reset to 0 by the ei instruction. its value is also modified by the reti instruction or ldsr instruction when referencing the psw. non-maskable interrupt and exceptions are acknowledged regardless of this flag. when a maskable interrupt is accepted, id flag is automatically set to 1 by hardware. interrupt requests generated during accept disabled (id = 1) can be accepted if the ifn bit of the icn register is set (1) and the id flag is reset (0). address fffff166h ispr 7 ispr7 at reset 00h 6 ispr6 5 ispr5 4 ispr4 3 ispr3 2 ispr2 1 ispr1 0 ispr0 31 10 z psw 2 s 3 ov 4 cy 5 sat 6 id 7 ep 8 np at reset 00000020h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
86 chapter 5 interrupt/exception processing function 5.4 software exception the software exception is generated when the cpu executes the trap instruction, and can always be accepted. trap instruction format: trap vector (where vector is 0 to 1fh) 5.4.1 operation if the software exception occurs, the cpu performs the following processing, and transfers control to the handler routine: (1) saves the value of pc to eipc. (2) saves the current psw to eipsw. (3) writes an exception code to the lower 16 bits (eicc) of ecr (interrupt source). (4) sets the ep and id bits of psw. (5) loads the vector address (00000040h or 00000050h) of the software exception routine in the pc, and transfers control. figure 5-9 illustrates how the software exception is processed. figure 5-9. software exception processing the vector address is determined by the operand of the trap instruction. if the operand is 0 to 0fh, the vector address is 00000040h; if the operand is 10h to 1fh, it is 00000050h. trap instruction eipc eipsw ecr. eicc psw. ep psw. id pc restored pc psw exception code 1 1 vector address cpu processing exception processing <- <- <- <- <- <-
87 chapter 5 interrupt/exception processing function 5.4.2 restore to restore or return execution from the software exception service routine, the reti instruction is used. operation of reti instruction when the reti instruction is executed, the cpu performs the following steps, and transfers control to the address of the restored pc. (1) restores the values of pc and psw from eipc and eipsw because the ep bit of psw is 1. (2) transfers control to the address of the restored pc and psw. figure 5-10 illustrates the processing of the reti instruction. figure 5-10. reti instruction processing caution when the psw.ep bit and psw.np bit have been changed using the ldsr instruction during the software exception interrupt processing, to restore the values of pc and psw when normal execution returns via the reti instruction, it is necessary to return the value of psw.ep to 1 immediately before the reti instruction is executed using the ldsr instruction. remark the solid lines indicate the cpu processing. reti instruction original processing restored pc psw <- eipc <- eipsw psw. ep 1 0 1 0 pc psw <- fepc <- fepsw psw. np
88 chapter 5 interrupt/exception processing function 5.4.3 ep flag the ep flag in the psw is a status flag used to indicate that exception processing is in progress. it is set when an exception occurs. bit position bit name function 6 ep exception pending indicates that trap processing is in progress 0: exception processing is not in progress 1: exception processing is in progress 5.5 exception trap the exception trap is an interrupt that is requested when illegal execution of an instruction takes place. in the v852, an illegal op code exception (ilgop: illegal opcode trap) is considered as an exception trap. illegal op code exception: occurs if the subop code field of an instruction to be executed next is not a valid op code. 5.5.1 illegal op code definition an illegal op code is defined to be a 32-bit word with bits 5 to 10 being 111111b and bits 23 to 26 being 0011b to 1111b. x : dont care 31 10 z psw 2 s 3 ov 4 cy 5 sat 6 id 7 ep 8 np at reset 00000020h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 16 20 26 x 27 21 22 23 31 0 13 12 11 10 5 4 xx xx 1 11111 xxx xx xxx xx xx xxxxx 0 1 0 1 1 1 1 1
89 chapter 5 interrupt/exception processing function 5.5.2 operation if an exception trap occurs, the cpu performs the following processing, and transfers control to the handler routine: (1) saves the value of restored pc to eipc. (2) saves the current psw to eipsw. (3) writes an exception code (0060h) to the lower 16 bits (eicc) of ecr. (4) sets the ep and id bits of psw. (5) loads the vector address (00000060h) for the exception trap routine to the pc, and transfers control. figure 5-11 illustrates how the exception trap is processed. figure 5-11. exception trap processing exception trap (ilgop) occurs eipc eipsw ecr. eicc psw. ep psw. id pc <- restored pc <- psw <- exception code <- 1 <- 1 <- 00000060h cpu processing exception processing
90 chapter 5 interrupt/exception processing function 5.5.3 restore to restore from the exception trap, the reti instruction is used. operation of reti instruction when the reti instruction is executed, the cpu performs the following processing, and transfers control to the address of the restored pc. (1) restores the values of pc and psw from eipc and eipsw because the ep bit of psw is 1. (2) transfers control to the address of the restored pc and psw. figure 5-12 illustrates the processing of the reti instruction. figure 5-12. reti instruction processing caution when the psw.ep bit and psw.np bit have been changed using the ldsr instruction during the exception trap interrupt processing, to restore the values of pc and psw when normal execution returns via the reti instruction, it is necessary to return the value of psw.ep to 1 immediately before the reti instruction is executed using the ldsr instruction. remark the solid lines indicate the cpu processing. reti instruction original processing restored pc psw <- eipc <- eipsw psw. ep 1 0 1 0 pc psw <- fepc <- fepsw psw. np
91 chapter 5 interrupt/exception processing function 5.6 priority control 5.6.1 priorities of interrupts and exceptions reset nmi int trap ilgop reset * * * * nmi x <- <- <- int x - <- <- trap x -- <- ilgop x --- reset : reset nmi : non-maskable interrupt int : maskable interrupt trap : software exception ilgop : illegal code exception * : item on the left ignores the item above. x : item on the left is ignored by the item above. - : item above is higher than the item on the left in priority. <- : item on the left is higher than the item above in priority. 5.6.2 multiple interrupt processing multiple interrupt processing is a function which allows the nesting of interrupts. if a higher priority interrupt is generated and accepted, it will be allowed to stop a current interrupt service routine in progress. if an interrupt with a lower or equal priority is generated and a service routine is currently in progress, the later interrupt will be kept pending. multiple interrupt processing control is performed while an interrupt service routine is currently in progress and the interrupts are kept enabled (id = 0). if a maskable interrupt or exception is generated and accepted while a prior interrupt routine is under progress, the higher priority interrupting routine must save the current contents of eipc and eipsw to allow proper restoration when the routine ends. programming examples used for interrupt nesting are shown in the following code fragments:
92 chapter 5 interrupt/exception processing function (1) to accept maskable interrupts in service routine service routine of maskable interrupt or exception ... ... ? saves eipc to memory or register ? saves eipsw to memory or register ? ei instruction (enables interrupt acceptance) ... ... <- accepts interrupt such as intp input ... ... ? di instruction (disables interrupt acceptance) ? restores saved value to eipsw ? restores saved value to eipc ? reti instruction (2) to generate exception in service program service program of maskable interrupt or exception ... ... ? saves eipc to memory or register ? saves eipsw to memory or register ... ? trap instruction <- accepts exception such as trap instruction ? illegal op code <- accepts exception such as illegal op code ... ? restores saved value to eipsw ? restores saved value to eipc ? reti instruction priorities 0 to 7 (0 is the highest) can be programmed for each maskable interrupt request for multiple interrupt processing control. to set a priority level, write values to the xxprn0 to xxprn2 bits of the interrupt request control register (xxicn) corresponding to each maskable interrupt request. at reset, the interrupt request is masked by the xxmkn bit, and the priority level is set to 7 by the xxprn0 to xxprn2 bits. priorities of maskable interrupts (high) level 0 > level 1 > level 2 > level 3 > level 4 > level 5 > level 6 > level 7 (low) interrupt processing that has been suspended as a result of multiple interrupt processing is resumed after the interrupt processing of the higher priority has been completed and the reti instruction has been executed. a pending interrupt request is accepted after the current interrupt processing has been completed and the reti instruction has been executed. caution the maskable interrupts are not accepted but pended in non-maskable interrupt processing routine (time until the reti instruction is executed).
93 chapter 5 interrupt/exception processing function 5.7 interrupt latency time the interrupt latency time is defined as the time measured between the generation of the interrupt request and the execution of the first instruction in the corresponding interrupt service routine. the following describes the interrupt latency time. figure 5-13. pipeline operation upon reception of interrupt request (outline) interrupt latency time (system clock) condition internal interrupt external interrupt minimum 11 13 except when: ? in idle/stop mode ? external bus is accessed maximum 18 20 ? two or more interrupt request non-sample instructions are executed in succession ? accessed interrupt control register 5.8 periods where interrupt is not acknowledged an interrupt is acknowledged while an instruction is being executed. however, no interrupt is acknowledged between interrupt request non-sample instruction and next instruction. interrupt request non-sample instruction ? ei instruction ? di instruction ? ldsr reg2, 0 x 5 instruction (vs. psw) if id ex mem wb 7 to 14 system clocks 4 system clocks system clock interrupt request instruction 1 instruction 2 instruction 3 interrupt acceptance operation instruction (first instruction of interrupt processing routine) int1 to int4 : interrupt acceptance processing ifx : instruction fetch to be invalid idx : instruction decode to be invalid if id ex mem wb ifx idx ifx int1 int2 int3 int4
94 chapter 5 interrupt/exception processing function [memo]
95 chapter 6 clock generator function chapter 6 clock generation function the clock generator produces and controls the internal system clock ( f ) which is supplied to all the internal hardware units including the cpu. 6.1 features multiplication function by pll (phase locked loop) synthesizer clock source ? oscillation through oscillator connection: f xx = x f , f xx = x f ? external clock (pll mode): f xx = f , f xx = f ? external clock (direct mode): f xx = 2 f power save mode ? halt mode ? idle mode ? software stop mode clock output inhibit function 6.2 configuration f vco : vco oscillation frequency (= 2 ? fxx: pllsel = 0), (= 10 ? fxx: at pllsel = 1) f : internal system clock frequency (= 1/2 ? f vco : in pll mode) internal system clock frequency (= 1/2 ? fxx: in direct mode) osc : oscillator (pll mode only) pfc : phase frequency comparator scf : switched capacitor filter vco : voltage-controlled oscillator frequency divider circuit (=1/4: pllsel = 0), (=1/20: pllsel = 1) 1 5 1 1 1 5 1 1 osc 1 2 pfc scf vco 1 2 x1 (f xx ) x2 cksel pllsel frequency divider circuit pll synthesizer in direct mode (f xx ) (f vco ) in pll mode f
96 chapter 6 clock generator function 6.3 selecting input clock the clock generator consists of a clock oscillator and a pll synthesizer. it can generate, for example, at pllsel = 1 a 25-mhz system clock when a 5-mhz crystal resonator or ceramic resonator is connected across the x1 and x2 pins. an external clock can be directly connected to the oscillator circuit. in this case, input the clock signal to the x1 pin, and leave the x2 pin open. the clock generator has two operation modes: pll and direct modes, which are selected by the cksel pin, as shown in the table below. cksel operation mode 0 pll mode 1 direct mode caution the cksel pin level should never be changed during operation. the v852 may not operate correctly. 6.3.1 direct mode in the direct mode, an external clock with a frequency two times higher than that of the system clock is input. because osc and pll synthesizer do not operate, the power dissipation can be significantly reduced. this mode is used mainly in applications where the v852 must operate on a relatively low frequency. to minimize the influence by noise, it is recommended that the frequency of the external clock, fxx, be kept to within 32 mhz (system clock f = 16 mhz). 6.3.2 pll mode in the pll mode, an external clock is input by connecting an external oscillator, which is multiplied by the pll synthesizer to generate system clock ( f ). the system clock ( f ) can be selected between mutiplication by 1 (1 f xx ) or by 5 (5 f xx ) of the external resonator or external clock frequency (f xx ). (refer to 2.3.1. (12) pllsel ) pllsel f 0f xx 15 f xx caution fix the pllsel pin so that the input level of this pin cannot be changed during operations (changes in input levels during operations may lead to incorrect operations). the pllsel pin has no function when the direct mode (cksel = 1) is set using the cksel pin. leave it as an unused pin.
97 chapter 6 clock generator function in the pll mode, if the external oscillator or external clock source fails, the clock generator continues to provide the internal system clock ( f ) based on the free-running frequency of the vco. in this mode, the internal system clock f operates at about 1 mhz (target). example of clock in pll mode pllsel system clock frequency ( f ) [mhz] external oscillator/external clock frequency (f xx ) [mhz] 0 25.000 ( f = f xx ) 20.000 16.384 1 25.000 5.0000 ( f = 5 f xx ) 20.000 4.0000 16.384 3.2768
98 chapter 6 clock generator function 6.4 pll stabilization following a power-on reset or when exiting the software stop mode, an amount of time is required for the pll to phase lock at a fixed frequency and stabilize. this required time is pll lock-up time. the status in which the frequency is not stable is called unlock status and the status in which it has been stabilized is called lock status. two system status flags are available to check with the stabilization of the pll frequency: unlock flag that indicates the stabilization status of the pll frequency, and prerr flag that indicates occurrence of a protection error (for the details of the prerr flag, refer to 6.5.2 (2) command register (prcmd) ). the sys register, which contains these unlock and preerr flags, can be read/written in 8- or 1-bit units. bit position bit name function 0 unlock unlock status flag this is read-only flag and indicates unlock status of pll. it holds 0 as long as lock up status is maintained, and is not initialized even if system is reset. 0 : indicates lock status 1 : indicates unlock status remark for the description of the prerr flag, refer to 6.5.2 (2) command register (prcmd) . if the unlock status condition should arise, due to a power or clock source failure, the unlock flag should be checked to verify that the pll has stabilized before performing any execution speed dependent operations, such as real-time processing. the static processing such as setting of the on-chip hardware units and initialization of the register data and memory data, however, can be executed before the unlock flag is reset. the following is the relationship between the oscillation stabilization time (stabilization time of input waveform after resonator start oscillating) and pll lock-up time (a time required for frequency stabilization) if a resonator is used. oscillation stabilization time < pll lock-up time address fffff078h sys 7 0 at reset 0000000xb 6 0 5 0 4 prerr 3 0 2 0 1 0 0 unlock
99 chapter 6 clock generator function 6.5 power save control 6.5.1 general the v852 has following power save modes. (1) halt mode in this mode, the clock generator (oscillator and pll synthesizer) continues operation, but the operating clock of the cpu stops. the internal peripherals continue to function in reference to the internal system clock. the total power consumption of the system can be reduced through intermittent operations between normal operation and the halt mode. the halt mode is entered by a dedicated instruction (halt instruction). (2) idle mode in this mode, both the cpu clock and the internal system clock are stopped to further reduce power con- sumption. however, since the clock generator continues to run, normal operation can resume without having to wait for the oscillator and pll circuits to stabilize. the idle mode is entered by programming the psc register. the idle mode stands between the stop and halt modes in terms of clock stabilization time and power consumption, and is used in applications where the clock stabilization time should be eliminated but low power consumption is required. (3) software stop mode in this mode, the cpu clock, the internal system clock, and the clock generator are stopped, reducing power consumption to only the leakage current. in this state, power consumption is minimized. (a) in pll mode the software stop mode is entered by programming the psc register. as soon as the oscillator circuit stops, the clock output of the pll synthesizer is stopped. after the software stop mode has been released, it is necessary to allow for stabilization time of the oscillator and system clock. moreover, the lock up or stabilization time of the pll may also be necessary, depending on the application. however, when the processor operates on an external clock, the need for oscillation stabilization time of the oscillator will become unnecessary. (b) in direct mode to stop the clock, fix the x1 pin to the low level. the pll lock up or stabilization time is not reqired to allow in the direct mode. (4) clock output inhibit output of the system clock from the clkout pin is disabled.
100 chapter 6 clock generator function the operations of the clock generator in the normal, halt, idle, and software stop modes are shown in table 6-1. by combining and selecting the mode ideal for a specific application, the power consumption of the system can be effectively reduced. table 6-1. operation of clock generator by power save control pll mode normal halt x idle xx stop x x x x external clock normal x halt x x idle x xx stop x x x x direct mode normal x x halt x x x idle x x x x stop x x x x : operates x : stops status transition diagram oscillation by resoantor clock supply to peripheral i/o oscillator circuit (osc) clock source clock supply to cpu standby mode pll synthesizer normal software stop idle halt released by reset or nmi input stop mode is entered released by reset, nmi input, or maskable interrupt request released by reset or nmi input idle mode is entered halt mode is entered
101 chapter 6 clock generator function 6.5.2 control registers (1) power save control register (psc) this is an 8-bit register that controls the power save mode. it can be written only by a specific combination of instruction sequences so that its contents are not written by mistake due to erroneous program execution. this register can be read/written in 8- or 1-bit units. bit position bit name function 7, 6 dclkn disable clkout (n = 1, 0) specifies operation mode of clkout pin dclk1 dclk0 mode 0 0 normal output mode 0 1 rfu (reserved) 1 0 rfu (reserved) 1 1 clock output inhibit mode 5 tbcs time base count select selects clock of time base counter 0: fxx/2 8 1: fxx/2 9 for details, refer to explanation of time base counter (tbc) in section 6.6 specifying oscillation stabilization time . 4 cesel crystal/external select specifies functions of x1 and x2 pins 0: oscillator connected to x1 and x2 pins 1: external clock connected to x1 pin when cesel = 1, the feedback loop of the oscillation circuit is cut so that the leakage current can be avoided during stop mode and the oscillation stabilization time by the time base counter (tbc) after the stop mode is released is not counted. 2 idle idle mode specifies idle mode. when 1 is written to this bit, idle mode is entered. when idle mode is released, this bit is automatically reset to 0. 1 stp stop mode specifies software stop mode. when 1 is written to this bit, stop mode is entered. when stop mode is released, this bit is automatically reset to 0. address fffff070h psc 7 dclk1 at reset 00h 6 dclk0 5 tbcs 4 cesel 3 0 2 idle 1 stp 0 0
102 chapter 6 clock generator function the psc register is programmed in the following special sequence: <1> the interrupt disable is set (psw np bit is set to 1). <2> any 8-bit data is written in the command register (prcmd). <3> the setting data is written in the psc register (using the following instructions). ? store instruction (st/sst instruction) ? bit manipulation instruction (set1/clr1/not1 instruction) <4> the interrupt disable is released (psw np bit is set to 0). <5> the nop instruction (2 or 5 instructions) is inserted. no special sequence is necessary for reading the psc register. cautions 1. if interrupts are accepted in the time between the prcmd issue (<2>) and the psc register writing (<3>) directly after, psc register is not written and protection error (sys register prerr bit is 1) is generated in some cases. therefore, set the psw np bit to 1 (<1>) and disable the int/nmi acceptance. the same applies when the bit manipulation instruction is used to set the psc register. insert the nop instruction (<5>) as the dummy instruction so that the routine is executed correctly after the stop/idle mode is released. if the psw id bit value is not to be changed by the execution of the instruction which returns the np bit to 0 (<4>), insert two nop instructions. if it is to be changed, insert five. the following are examples. [example] ldsr rx,5 ; np bit = 1 st.b r0,prcmd [r0] ; writing in prcmd st.b rd,psc [r0] ; sets psc register ldsr ry,5 ; np bit = 0 nop ; dummy instruction (2 or 5 instructions) . . . nop (next instruction) ; execution routine after stop/idle mode has been released . . . rx: value written in psw ry: value written back to psw rd: value set to psc when saving the psw value, it is necessary to transfer the psw value before setting the np bit to the ry register. 2. the instruction (<4> interrupt disable release, <5> nop instruction) after the store instruction for the psc register to be set to the software stop mode and idle mode are executed before each power save mode is set.
103 chapter 6 clock generator function (2) command register (prcmd) the command register protects the psc register from being illegally written so that the application system does not stop due to erroneous program execution. only data written first to the psc register after the prcmd register has been written becomes valid. because the register value can be rewritten only in a fixed sequence, illegal write operations are prevented. the command register can be only written in 8-bit units (when this register is read, undefined data is read). bit position bit name function 7 to 0 reg7 to reg0 registration code registration code (any 8-bit data) occurrence of an illegal store operation can be checked by the prerr flag of the system status register (sys). bit position bit name function 4 prerr protection error flag indicates that psc register is not written in the correct sequence and that a protection error has occurred. 0: protection error does not occur 1: protection error occurs remark for the description of the unlock flag, refer to 6.4 pll stabilization . operation conditions of prerr flag set condition (prerr = 1) : <1> if the store instruction to the peripheral i/o most recently executed does not write data to the prcmd register, but to the psc register <2> if the first store instruction executed after the write operation to the prcmd register is to a peripheral i/o register except psc register. reset condition (prerr = 0) : <1> when 0 is written to the prerr flag of the sys register. <2> at system reset address fffff170h prcmd 7 reg7 at reset undefined 6 reg6 5 reg5 4 reg4 3 reg3 2 reg2 1 reg1 0 reg0 address fffff078h sys 7 0 at reset 0000000xb 654 prerr 3210 unlock 00 000
104 chapter 6 clock generator function 6.5.3 halt mode (1) entering and operation status in the halt mode, the clock generator (oscillator circuit and pll synthesizer) operates, while the operating clock of the cpu stops. the internal peripherals continue to function in reference to the internal system clock. by entering the halt mode during the idle time of the cpu, the total power consumption of the system can be reduced. this mode is entered by the halt instruction. in the halt mode, program execution stops, but the contents of the registers and internal ram immediately before entering the halt mode are retained. the on-chip peripheral functions that are not dependent on the instruction processing of the cpu continue to operate. table 6-2 shows the status of each hardware unit in the halt mode. table 6-2. operating status in halt mode function operating status clock generator operates internal system clock operates cpu stops i/o line retained peripheral function operates internal data status of internal data before setting of halt mode, such as cpu registers, status, data, and internal ram contents, are retained. ad0 to ad15 high impedance note a16 to a23 retained note high-impedance when hldak = 0 lben, uben r/w dstb astb st0, st1 low-level output note hldak operates clkout clock output (when clock output is not inhibited) note the instruction fetch operation continues even after the halt instruction has been executed, until the internal instruction prefetch queue becomes full. after the queue has become full, the operation stops in the status indicated in the above table. external expansion mode high-level output note
105 chapter 6 clock generator function (2) releasing halt mode the halt mode can be released by a non-maskable interrupt request, unmasked maskable interrupt request, or the reset signal input. (a) releasing by interrupt request the halt mode is unconditionally released by the nmi request or an unmasked maskable interrupt request, regardless of the priority. however, if the halt mode is set in an interrupt processing routine, the operation differs as follows: (i) if an interrupt request with a priority lower than that of the interrupt request under execution is generated, the halt mode is released, but the newly generated interrupt request is not accepted. the new interrupt request is kept pending. (ii) if an interrupt request with a priority higher (including nmi request) than the interrupt request under execution is generated, the halt mode is released, and the interrupt request is also accepted. operation after halt mode has been released by interrupt request releasing source interrupt enable (ei) status interrupt disable (di) status nmi request branches to handler address maskable interrupt request branches to handler address executes next instruction or executes next instruction (b) releasing by reset signal input the same operation as the normal reset operation is performed.
106 chapter 6 clock generator function 6.5.4 idle mode (1) setting and operation status in this mode, both the cpu clock and the internal system clock are stopped to further reduce power consumption. however, since the clock generator continues to run, normal operation can resume without having to wait for the oscillator and pll circuit to stabilize. the idle mode is entered when the psc register is programmed by the store (st/sst) instruction or bit manipulation (set1/clr1/not1) instruction. execution of the program is stopped in the idle mode, but the contents of the registers and internal ram immediately before entering the idle mode are retained. the on-chip peripheral functions are stopped in this mode. external bus hold request (hldrq) is not accepted. table 6-3 shows the hardware status in the idle mode. table 6-3. operating status in idle mode function operating status clock generator operates internal system clock stops cpu stops i/o line retained peripheral function stops internal data status of all internal data immediately before idle mode is entered, such as cpu registers, status, data, and internal ram contents, are retained. ad0 to ad15 high-impedance a16 to a23 lben, uben r/w dstb astb st0, st1 hldak clkout low-level output external expansion mode
107 chapter 6 clock generator function (2) releasing idle mode the idle mode is released by the nmi signal input or reset signal input. (a) releasing by nmi signal input the nmi request is accepted and serviced as soon as the idle mode has been released. if the idle mode is entered in the nmi processing routine, however, only the idle mode is released, and the interrupt will not be accepted. the interrupt request is retained and kept pending. the interrupt processing that is started by the nmi signal input when the idle mode is released is treated in the same manner as a normal nmi interrupt that is processed (because there is only one vector address of the nmi interrupt). therefore, if it is necessary to distinguish between the two types of nmi interrupts, a software status should be defined in advance, and the status must be set before setting the idle flag by the store/bit manipulation instruction. by checking this status during the nmi interrupt processing, the nmi used to release the idle mode can be distinguished from the normal nmi. (b) releasing by reset signal input the same operation as the normal reset operation is performed.
108 chapter 6 clock generator function 6.5.5 software stop mode (1) entering and operaton status in this mode, the clock generator (oscillation circuit and pll synthesizer) is stopped, reducing power consumption to only leakage current. in this state, the whole system is stopped and power consumption is minimized. the software stop mode is entered by programming the psc register using the store (st/sst) or bit manipulation (set1/clr1/not1) instruction. it is necessary to ensure the oscillation stabilization time of the oscillator circuit after the software stop mode has been released, when the pll mode (cksel pin = 0) and the resonator connection mode (cesel bit = 0) are set. in the software stop mode, program execution is stopped, but all the contents of the registers and internal ram immediately before entering the stop mode are retained. the on-chip peripheral function also stops operation. table 6-4 shows the hardware status in the software stop mode. table 6-4. operating status in software stop mode function operating status clock generator stops internal system clock stops cpu stops i/o line note retained peripheral function note stops internal data status of all internal data immediately before software stop mode is set, such as cpu registers, status, data, and internal ram contents, are retained. ad0 to ad15 high-impedance a16 to a23 lben, uben r/w dstb astb st0, st1 hldak clkout low-level output note when the value of v dd is within the operating range. even if v dd drops below the minimum operating voltage, the contents of the internal ram can be retained if the data retention voltage v dddr is maintained. external expansion mode
109 chapter 6 clock generator function (2) releasing software stop mode the stop mode is released by the nmi signal input or reset signal input. it is necessary to ensure the oscillation stabilization time when releasing from the stop mode if the status is in the operating condition of the oscillator circuit (pll mode (cksel pin = 0) and in the resonator connection mode (cesel bit = 0)). when using in the prom programming mode, refer to 11.6 cautions on stop mode release when using external clock . (a) releasing by nmi signal input when the stop mode is released by the nmi signal, the nmi request is also accepted. if the stop mode is set in an nmi processing routine, however, only the stop mode is released, and the interrupt is not accepted. the interrupt request is retained and kept pending. caution if the external clock is input to the x1 pin, supply the external clock more than 150 m s before releasing by the nmi input. nmi interrupt processing on releasing stop mode the interrupt processing that is started by the nmi signal input when the stop mode is released is treated in the same manner as a normal nmi interrupt that is processed (because there is only one vector address of the nmi interrupt). therefore, if it is necessary to distinguish between the two types of nmi interrupts, a software status should be defined in advance, and the status must be set before setting the stop flag by the store/bit manipulation instruction. by checking this status during the nmi interrupt processing, the nmi used to release the stop mode can be distinguished from the normal nmi. (b) releasing by reset signal input the same operation as the normal reset operation is performed. caution if the external clock is input to the x1 pin, supply the clock and maintain the low level width of the reset pin for more than 150 m s.
110 chapter 6 clock generator function 6.6 specifying oscillation stabilization time the time required for the oscillator circuit to become stabilized after the stop mode has been released can be specified in the following two ways: (1) by using internal time base counter (nmi signal input) when the valid edge is input to the nmi pin, the stop mode is released. when the inactive edge is input to the pin, the time base counter (tbc) starts counting, and the time required for the clock output from the oscillator circuit to become stabilized is specified by that count time. oscillation stabilization time ~ (active level width after valid edge of nmi input has been detected) + (count time of tbc) after a specific time has elapsed, the system clock output is started, and execution branches to the vector address of the nmi interrupt. normally, the nmi pin should be kept at the inactive level (e.g. at a high level when the valid edge is specified to be the falling edge). if an operation to enter the stop mode is performed while a valid edge has been input to the nmi pin before the cpu accepts the interrupt, the stop mode will immediately be released. program execution is immediately started if the clock generator is in the direct mode (cksel = 1) or is driven by external clock (cesel = 1). if the clock generator is in the pll mode (cksel = 0) and is driven by a resonator (cesel = 0), program execution is started after the oscillation stabilization time specified in the time base counter has elapsed, following the inactive edge input to the nmi pin. oscillating waveform stop mode set oscillator circuit stops system clock (clkout output) stop status nmi input count time of time base counter
111 chapter 6 clock generator function (2) to specify time by signal level width (reset signal input) the stop mode is released when the falling edge is input to the reset pin. the time required for the clock output from the oscillator circuit to become stabilized is specified by the low- level width of the signal input to the reset pin. after the rising edge has been input to the reset pin, operation of the internal system clock begins, and execution branches to the vector address that is used when the system is reset. oscillating waveform stop mode set oscillator circuit stops system clock (clkout output) stop status internal system reset signal oscillation stabilization time secured b y reset reset signal undefined
112 chapter 6 clock generator function time base counter (tbc) the time base counter is used to secure the oscillation stabilization time of the oscillator circuit when the software stop mode is released. ? when external clock is connected (cesel bit of the psc register = 1) oscillation stabilization time count is not performed by tbc and the program execution starts immediately after the stop mode cancelation. ? when resonator is connected (cesel bit of the psc register = 0) oscillation stabilization time is counted by tbc after the cancelation of the stop mode and the program execution starts after counting finish. the count clock of tbc is selected by the tbcs bit of the psc register, and the following count time can be set: table 6-5. example of count time (a) at multiplication by 1 (pllsel = 0) count time tbcs count clock fxx = 13.500 mhz fxx = 20.000 mhz fxx = 25.000 mhz f = 13.500 mhz f = 20.000 mhz f = 25.000 mhz 0 fxx/2 8 19.4 ms 13.1 ms 10.4 ms 1 fxx/2 9 38.8 ms 26.2 ms 20.9 ms fxx : external oscillator frequency f : internal system clock frequency (b) at multiplication by 5 (pllsel = 1) count time tbcs count clock fxx = 3.2768 mhz fxx = 4.0000 mhz fxx = 5.0000 mhz f = 16.384 mhz f = 20.000 mhz f = 25.000 mhz 0 fxx/2 8 20.0 ms 16.3 ms 13.1 ms 1 fxx/2 9 40.0 ms 32.7 ms 26.2 ms fxx : external oscillator frequency f : internal system clock frequency figure 6-1. block configuration tbc f xx /2 8 f xx /2 9 oscillation stabilization time control circuit overflow 10 bits : at multiplication by 1 8 bits : at multiplication by 5
113 chapter 6 clock generator function 6.7 clock output control the operation mode of the clkout pin can be selected by the dclk0 and dclk1 bits of the psc register. by using this operation mode in combination with the halt, idle, or stop mode, the power dissipation can be effectively reduced (for how to write these bits, refer to 6.5.2 control registers ). clock output inhibit mode the clock output from the clkout pin is inhibited. this mode is ideal for single-chip mode systems or systems that fetch instructions to external expansion devices or asynchronously access data. because the operation of clkout is completely stopped in this mode, the power dissipation can be minimized and radiation noise from the clkout pin can be suppressed. clkout (normal mode) (fixed to low level) clkout (clock output inhibit mode) l
114 chapter 6 clock generator function [memo]
115 chapter 7 timer/counter function (real-time pulse unit) chapter 7 timer/counter function (real-time pulse unit) 7.1 features measures pulse intervals and frequency, and outputs programmable pulse ? 16-bit measurement possible ? generates pulses of various shapes (interval pulse, one-shot pulse) timer 1 ? 16-bit timer/event counter ? count clock source: 2 types (divided system clock and external pulse input) ? capture/compare register: 4 ? count clear pin: tclr1 ? interrupt source: 5 types ? external pulse output: 2 timer 4 ? 16-bit interval timer ? count clock selected from divided system clock ? compare register: 1 ? interrupt source: 1
116 chapter 7 timer/counter function (real-time pulse unit) 7.2 basic configuration the basic configuration of the real-time pulse unit (rpu) is shown in the table below. table 7-1. configuration of rpu timer count clock register read/write other function timer 1 tm1 read intov1 C C external clear cc10 read/write intcc10 intp10 to10 (s) C cc11 read/write intcc11 intp11 to10 (r) C cc12 read/write intcc12 intp12 to11 (s) C ti1 pin input cc13 read/write intcc13 intp13 to11 (r) C timer 4 tm4 read C C C C cm4 read/write intcm4 C C C remark f : system clock sr : set/reset generated interrupt signal timer output sr capture trigger f / 32 f / 64 f / 128 f / 256 f / 2 f / 4 f / 8 f / 16 f / 32 f / 64
117 chapter 7 timer/counter function (real-time pulse unit) (1) timer 1 (16-bit timer/event counter) notes 1. internal count clock frequency 2. external count clock frequency 3. reset priority remark f indicates the system clock. (2) timer 4 (16-bit interval timer) note internal count clock remark f indicates the system clock. cm4 intcm4 tm4 (16 bits) m m/16 m/32 f f f /2 /4 /8 f f f clear & start note intp10 intp11 intp12 intp13 edge detection cc10 cc11 cc12 cc13 s intcc10 intcc11 to10 r q q s to11 r q q intcc12 intcc13 note 3 note 3 tm1 (16 bits) edge detection m m m/4 m/8 m/16 /2 /4 tclr1 intov1 note 1 edge detection edge detection edge detection edge detection clear & start f f f note 2 ti1 f f f f clear & start
118 chapter 7 timer/counter function (real-time pulse unit) 7.2.1 timer 1 (1) timer 1 (tm1) tm1 functions as a 16-bit free-running timer or event counter for external signals. timer 1 is used to measure cycles and frequency, and also for pulse generation. tm1 can be only read in 16-bit units. tm1 counts up the internal count clock or external count clock. the tm1 is started or stopped by the ce1 bit of timer control register 1 (tmc1). whether the internal or external count clock is used is specified by the tmc1 register. caution count clock cannot be changed during the timer operation. (a) when external count clock is selected tm1 operates as an event counter. the valid edge is specified by timer unit mode register 1 (tum1), and tm1 counts up the signal input from the ti1 pin (b) when internal count clock is selected tm1 operates as a free-running timer. the count clock selects the division by the prescaler by the tmc1 register from f /2, f /4, f /8, f /16, f /32, or f /64. when the timer overflows, an overflow interrupt can be generated. the timer can be stopped after an overflow has occurred, if so specified by the tum1 register. the timer can be cleared and started by external tclr1 input. at this time, the prescaler is cleared at the same time. as a result, the time from the tclr1 input to the first count up by the timer is held constant, according to the division ratio of the prescaler. the operation is set by the tum1 register. when the reset signal is input, all the bits of tm1 are cleared to 0. address fffff250h tm1 at reset 0000h 15 0
119 chapter 7 timer/counter function (real-time pulse unit) (2) capture/compare registers 10 to 13 (cc10 to cc13) capture/compare registers are 16-bit registers and are connected to the tm1. these registers can be used as capture or compare register depending on the specification of the timer unit mode register 1 (tum1). they can be read/written in 16-bit units. (a) when used as capture register when a capture/compare register is used as a capture register, it detects the valid edge of the corresponding external interrupt (intpn (n = 10 to 13)) as a capture trigger. timer 1 latches the count value in synchronization with the capture trigger (capture operation). the capture operation is performed asynchronously with the count clock. the latched value is held by the capture register, until the next capture operation is performed. if the capture (latch) timing of the capture register contends with a register write operation by an instruction, the latter takes precedence, and the capture operation is ignored. the valid edge of the external interrupt (rising, falling, or both edges) can be selected by external interrupt mode register (intm2). when a capture/compare register is used as a capture register, and when the valid edge of intpn is detected, an interrupt is generated. during this time, no interrupt can be generated by a coincidence signal intccn (n = 10 to 13) of a compare register. (b) when used as compare register when a capture/compare register is used as a compare register, it compares its contents with the value of the timer at each clock tick. when the two values match, a coincidence signal intccn is generated. the compare register is equipped with a set/reset output function. this function synchronizes with the generation of the coincidence signal and sets or resets the corresponding timer output. the interrupt source depends on the register mode, whether it is used as a capture or compare register. when used as a compare register, coincidence signal intccn or the valid edge of intpn can be selected as an interrupt signal, depending on the specification of the tum1 register. when intpn is selected, an external interrupt from intpn is acknowledged and timer outputs by compare registers set/reset output function are enabled. address fffff252h cc10 at reset undefined 15 0 address fffff254h cc11 at reset undefined 15 0 address fffff256h cc12 at reset undefined 15 0 address fffff258h cc13 at reset undefined 15 0
120 chapter 7 timer/counter function (real-time pulse unit) 7.2.2 timer 4 (1) timer 4 (tm4) tm4 is a 16-bit timer and is mainly used as an interval timer for software. this timer can be only read in 16-bit units. tm4 is started or stopped by the ce4 bit of the timer control register 4 (tmc4). the count clock selects the divider of the prescaler by the tmc4 register from f /32, f /64, f /128, or f /256. all the bits of tm4 are cleared to 0 by the reset input. cautions 1. when the value of the timer coincides with the value of the compare register, the timer is cleared by the next clock tick. when the division ratio is large, the timer value may not be cleared to 0 yet, even if the timer is read immediately after the occurrence of the coincidence signal interrupt. 2. count clock cannot be changed during the timer operation. (2) compare register 4 (cm4) cm4 is a 16-bit register and is connected to tm4. this register can be read/written in 16-bit units. cm4 compares its value with the value of tm4 at each clock tick of tm4, and generates an interrupt (intcm4) when the two values match or coincide with each other. tm4 is cleared in synchronization with this coincidence. address fffff350h tm4 at reset 0000h 15 0 address fffff352h cm4 at reset undefined 15 0
121 chapter 7 timer/counter function (real-time pulse unit) 7.3 control registers (1) timer unit mode register 1 (tum1) tum1 is a register that controls the operation of tm1, and specifies the operation mode of the capture/compare registers. this register can be read/written in 16-bit units. bit position bit name function 13 ost overflow stop specifies operation of timer after occurrence of overflow. this flag is valid only for tm1. 0: timer continues counting after overflow has occurred. 1: timer holds 0000h and stops after overflow has occurred. at this time, ce1 bit of tmc1 register remains 1. timer resumes counting when following operation is performed: when eclr1 = 0: writing 1 to ce1 bit when eclr1 = 1: trigger input to timer clear pin (tclr1) 12 eclr1 external input timer clear enables clearing tm1 by external clear input (tclr1) 0: tm1 is not cleared by external input 1: tm1 is cleared by external input after tm1 has been cleared, it starts counting. 11, 10 tes11, tes10 ti1 edge select specifies valid edge of external clock input (ti1) tes11 tes10 valid edge 0 0 falling edge 0 1 rising edge 1 0 rfu (reserved) 1 1 both rising and falling edges 9, 8 ces11, ces10 tclr1 edge select specifies valid edge of external clear input (tclr1) ces11 ces10 valid edge 0 0 falling edge 0 1 rising edge 1 0 rfu (reserved) 1 1 both rising and falling edge address fffff240h tum1 8 0 at reset 0000h 6 0 5 3210 ims10 4 9 10 11 12 13 14 15 7 ims11 ims12 ims13 cms10 cms11 cms12 cms13 ces10 ces11 tes10 tes11 eclr1 ost
122 chapter 7 timer/counter function (real-time pulse unit) bit position bit name function 7 to 4 cms13 to capture/compare mode select cms10 selects operation mode of capture/compare registers (ccn) 0: capture register. however, capture operation is performed only when ce1 of tmc1 register = 1. 1: compare register 3 to 0 ims13 to ims10 interrupt mode select selects intpn or intccn as interrupt source 0: uses coincidence signal of intccn of compare register as interrupt signal 1: uses external input signal intpn as interrupt signal remark n = 13 to 10
123 chapter 7 timer/counter function (real-time pulse unit) (2) timer control register 1 (tmc1) tmc1 controls the operation of tm1. this register can be read/written in 8- or 1-bit units. bit position bit name function 7 ce1 count enable controls timer operation. 0: timer stops at 0000h and does not operate. 1: timer performs count operation. however, it does not start counting when tum1.eclr1 = 1, until tclr1 signal is input. when tum1.eclr1 = 0, starting counting of timer by ce1 = 1 is triggered by writing 1 to ce1 bit. therefore, timer is not started even when tum1.eclr1 = 0 after ce1 has been set with tum1.eclr1 = 1. 4 eti external ti1 input specifies external or internal count clock. 0: f (internal) 1: ti1 (external) 3, 2 prs11, prs10 prescaler clock select selects internal count clock ( f m is intermediate clock) prs11 prs10 count clock 00 f m 01 f m/4 10 f m/8 11 f m/16 1 prm11 prescaler clock mode selects intermediate clock f m of count clock ( f is system clock). 0: f /2 1: f /4 caution do not change the count clock frequency while the timer operates. address fffff242h tmc1 7 ce1 at reset 00h 6 0 5 0 4 eti 3 prs11 2 prs10 1 prm11 0 0
124 chapter 7 timer/counter function (real-time pulse unit) (3) timer control register 4 (tmc4) tmc4 controls the operation of tm4. this register can be read/written in 8- or 1-bit units. bit position bit name function 7 ce4 count enable controls operation of timer. 0: timer stops at 0000h and does not operate. 1: timer performs count operation. 2 prs40 prescaler clock select selects internal count clock ( f m is intermediate clock). 0: f m/16 1: f m/32 1, 0 prm41, prm40 prescaler clock mode selects intermediate clock f m of count clock ( f is system clock). prm41 prm40 f m 00 f /2 01 f /4 10 f /8 1 1 rfu (reserved) caution do not change the count clock frequency while the timer operates. address fffff342h tmc4 7 ce4 at reset 00h 6 0 5 0 4 0 3 0 2 prs40 1 prm41 0 prm40
125 chapter 7 timer/counter function (real-time pulse unit) (4) timer output control register 1 (toc1) toc1 controls the timer output from the to10 and to11 pins. this register can be read/written in 8- or 1-bit units. bit position bit name function 7, 5 ento11, ento10 enable toxx pin xx = 11, 10 enables corresponding timer output (toxx). 0: timer output is disabled. the reverse phase level of active level specified in the alv bit (inactive level) is output from the corresponding toxx pin. even if coincidence signal is generated from corresponding compare register, level of toxx pin does not change. 1: timer output function is enabled. timer output changes when coincidence signal is generated from corresponding compare register. after the timer output has been enabled before the first coincidence signal is generated, the reverse phase level of active level specified in the alv bit is output. 6, 4 alv11, alv10 active level toxx pin xx = 11, 10 specifies active level of timer output. 0: active-low 1: active-high remark f/f of toxx output gives priority to reset. caution the toxx output is not changed by the external interrupt signal (intpn) (n = 10 to 13). when using toxx, specify a capture/compare register as a compare register (cmsn = 1) (n = 10 to 13). (5) external interrupt mode register 2 (intm2) if n (n = 10 to 13) of tm1 is used as a capture register, a valid edge of external interrupt intpn is used as a capture trigger. this valid edge can be specified with the intm2 register. for details, refer to section 5.3.6 external interrupt mode registers 1 and 2 (intm1 and intm2) . address fffff244h toc1 7 ento11 at reset 00h 6 alv11 5 ento10 4 alv10 3 0 2 0 1 0 0 0
126 chapter 7 timer/counter function (real-time pulse unit) (6) timer overflow status register (tovs) flags that indicate occurrence of an overflow from tm1 and tm4 are assigned to this register. this register can be read/written in 8- or 1-bit units. by testing and resetting the tovs register via software, occurrence of an overflow can be polled. bit position bit name function 4, 1 ovfn overflow flag tmn (n = 4, 1) overflow flag. 0: no overflow from tmn 1: overflow from tmn caution the invtov1 interrupt request signal is generated for the interrupt controller by synchronizing with the overflow from the tm1. however, the interrupt operations are independent from the tovs. overflow flags (ovf1) from the tm1 can be manipulated by the software like other overflow flags. at this time, the interrupt request flag (ovf1) in the interrupt controller for the intov1 will not be affected. the overflow flags will not be transmitted to the tovs register while accessing from the cpu. therefore, when overflows occur during reading of the tovs register, this overflow condition will be reflected the next time the tovs register is read, without changing the flag value. address fffff230h tovs 7 0 at reset 00h 6 0 5 0 4 ovf4 3 0 2 0 1 ovf1 0 0
127 chapter 7 timer/counter function (real-time pulse unit) 7.4 timer 1 operation 7.4.1 count operation timer 1 functions as a 16-bit free-running timer or event counter, as specified by timer control register 1 (tmc1). when it is used as a free-running timer, and when the count value of tm1 coincides with the value of the ccn (n = 10 to 13) register, an interrupt signal is generated, and timer output toxx (xx = 10, 11) can be set/reset. in addition, a capture operation that holds the current count value of tm1 and loads it into the register ccn, is performed in synchronization with the valid edge detected from the corresponding external interrupt request pin as an external trigger. the captured value is retained until the next capture trigger is generated. figure 7-1. basic operation of timer 1 7.4.2 selecting count clock frequency an internal or external count clock frequency can be input to timer 1. which count clock frequency is used is specified by the eti bit of the tmc1 register. caution do not change the count clock frequency while the timer operates. (1) internal count clock (eti bit = 0) an internal count clock frequency is selected by the prm11, prs11, and prs10 bits of the tmc1 register, from f /2, f /4, f /8, f /16, f /32, and f /64. prs11 prs10 prm11 count clock frequency 000 f /2 001 f /4 010 f /8 011 f /16 100 f /16 101 f /32 110 f /32 111 f /64 0001h 0002h 0003h fbfeh fbffh 0000h 0001h 0002h 0003h 0000h tm1 count starts ce1 <- 1 count disabled ce1 <- 0 count starts ce1 <- 1 count clock
128 chapter 7 timer/counter function (real-time pulse unit) (2) external count clock (eti bit = 1) the signal input to the ti1 pin is counted. at this time, timer 1 can operate as an event counter. the valid edge of ti1 is specified by the tes11 and tes10 bits of the tum1 register. tes11 tes10 valid edge 0 0 falling edge 0 1 rising edge 1 0 rfu (reserved) 1 1 both rising and falling edges 7.4.3 overflow if the tm1 register overflows as a result of counting the count clock frequency to ffffh, the ovf1 bit of the tovs register is set to 1, and an overflow interrupt (intov) is generated. after the overflow has occurred, the timer can be stopped by setting the ost bit of the tum1 register to 1. if the timer is stopped due to overflow, the counting operation is not resumed until ce is set to 1 by software. the operation is not affected even if ce1 is set to 1 during count operation. figure 7-2. operation after occurrence of overflow (when eclr1 = 0, ost = 1) tm1 intov1 0 ost 1 ce1 1 ce1 1 count starts overflow ffffh overflow ffffh
129 chapter 7 timer/counter function (real-time pulse unit) 7.4.4 clearing/starting timer by tclr1 input timer 1 usually starts the count operation when the ce1 bit of the tmc1 register is set to 1. it is also possible to clear tm1 and start the count operation by using external input tclr1. when the valid edge is input to tclr1 after eclr1 = 1, ost = 0, and ce1 is set to 1, the count operation is started. if the valid edge is input to tclr1 during operation, tm1 clears its value and then resumes the count operation (refer to figure 7-3 ). when the valid edge is input to tclr1 after eclr1 = 1, ost = 1, and ce1 is set to 1 from 0, the count operation is started. when tm1 overflows, the count operation is stopped once and is not resumed until the valid edge is input to tclr1. if the valid edge of tclr1 is detected during count operation, tm1 is cleared and continues counting (refer to figure 7-4 ). the count operation is not started if setting the ce1 to 1 after the overflow. figure 7-3. clearing/starting timer by tclr1 input (when eclr1 = 1, ost = 0) figure 7-4. relationships between clear/start by tclr1 input and overflow (when eclr1 = 1, ost = 1) tm1 intov1 0 eclr1 1 ce1 1 tclr1 tclr1 count starts overflow ffffh clear & start tm1 intov1 0 ce1 1 tclr1 1 tclr1 1 tclr1 1 count starts overflow ffffh
130 chapter 7 timer/counter function (real-time pulse unit) 7.4.5 capture operation a capture operation that captures and holds the count value of tm1 and loads it to a capture register in asynchronization with an external trigger can be performed. the valid edge from the external interrupt request input pin intpn (n = 10 to 13) is used as the capture trigger. in synchronization with this capture trigger signal, the count value of tm1 during counting, is captured and loaded to the capture register. the value of the capture register is retained until the next capture trigger is generated. interrupt signal intccn is generated from intpn input signal. table 7-2. capture trigger signal to 16-bit capture register (tm1) capture register capture trigger signal cc10 intp10 cc11 intp11 cc12 intp12 cc13 intp13 remark cc10 to cc13 are capture/compare registers. whether these registers are used as capture or compare registers is specified by timer unit mode register 1 (tum1). the valid edge of the capture trigger is set by external interrupt mode register (intm2). when both the rising and falling edges are specified as the capture trigger, the width of an externally input pulse can be measured. if either the rising or falling edge is specified as the capture trigger, the frequency of the input pulse can be measured. figure 7-5. example of tm1 capture operation (when both edges are specified) remark dn (n = 0, 1, 2, ...): count value of tm1 the capture operation is not performed even if the interrupt signal is input when ce1 is cleared to 0. tm1 count value interrupt request (intp10) capture register (cc10) count start ce1 <- 1 ovf1 <- 1 (overflow) d0 d1 d2 d1 d0 d2 ffffh
131 chapter 7 timer/counter function (real-time pulse unit) figure 7-6. example of tm1 capture operation tm1 ce1 n 0 n capture trigger cc10-cc13 intp10-intp13
132 chapter 7 timer/counter function (real-time pulse unit) 7.4.6 compare operation a comparison between the value in a compare register with the count value of tm1 can be performed. when the count value of tm1 coincides with the value of the compare register programmed in advance, a coincidence signal is sent to the output control circuit (refer to figure 7-7 ). the levels of the timer output pins (to10 and to11) can be changed by the coincidence signal, and an interrupt request signal can be generated at the same time. table 7-3. interrupt request signal from 16-bit compare register (tm1) compare register interrupt request signal cc10 intcc10 cc11 intcc11 cc12 intcc12 cc13 intcc13 remark cc10 to cc13 are capture/compare registers. whether these registers are used as capture or compare registers is specified by timer unit mode register 1 (tum1). figure 7-7. example of compare operation remark note that the coincidence signal is generated immediately after tm1 is incremented as shown above. count clock timer1 cc1 x coincidence detected n? n n + 1 n tm1
133 chapter 7 timer/counter function (real-time pulse unit) tm1 has two timer output pins: to10 and to11. the count value of tm1 is compared with the value of cc10. when the two values coincide, the output level of the to10 pin is set. the count value of tm1 is also compared with the value of cc11. when the two values coincide, the output level of the to10 pin is reset. similarly, the count value of tm1 is compared with the value of cc12. when the two values coincide, the output level of the to11 pin is set. the count value of tm1 is also compared with the value of cc13. when the two values coincide, the output level of to11 pin is reset. the output levels of the to10 and to11 pins can be specified by the toc1 register. figure 7-8. example of tm1 compare operation (set/reset output mode) tm1 count value 0 interrupt request (intcc10) interrupt request (intcc11) to10 pin ento10 <- 1 alv10 <- 1 cc10 cc11 ffffh ffffh cc11 cc10 cc10 count starts ce1 <- 1 ovf1 <- 1 (overflow) ovf1 <- 1 (overflow)
134 chapter 7 timer/counter function (real-time pulse unit) 7.5 timer 4 operation 7.5.1 count operation timer 4 functions as a 16-bit interval timer. the operation is specified by the timer control register 4 (tmc4). the operation of timer 4 counts the internal count clocks ( f /32 to f /256) specified by the prs40, prm41, and prm40 bits of the tmc4 register. if the count value of tm4 coincides with the value of cm4, the value tm4 is cleared while simultaneously a coincidence interrupt (intcm4) is generated. figure 7-9. basic operation of timer 4 7.5.2 selecting the count clock frequency an internal count clock frequency is selected by the prs40, prm40, and prm41 bits of the tmc4 register, from f /32, f /64, f /128, and f /256. caution do not change the count clock frequency while the timer operates. prs40 prm40 prm41 count clock frequency 00 0 f /32 00 1 f /64 01 0 f /128 0 1 1 rfu (reserved) 10 0 f /64 10 1 f /128 11 0 f /256 1 1 1 rfu (reserved) 7.5.3 overflow if tm4 overflows, the ovf4 bit of the tovs register is set to 1. 0000h 0001h 0002h 0003h fbfeh fbffh 0000h 0001h 0002h 0003h count clock tm4 count starts ce4 <- 1 count disabled ce4 <- 0 count starts ce4 <- 1
135 chapter 7 timer/counter function (real-time pulse unit) 7.5.4 compare operation a comparison can be performed with the counter value of tm4 and the compare register (cm4). when the count value of tm4 coincides with the value of the compare register, a coincidence interrupt (intcm4) is generated. as a result, tm4 is cleared to 0 at the next count timing (refer to figure 7-10 ). this function allows timer 4 to be used as an interval timer. cm4 can be also set to 0. in this case, a coincidence is detected when tm4 overflows and is cleared to 0, and intcm4 is generated. the value of tm4 is cleared to 0 at the next count timing, but intcm4 is not generated when a coincidence occurs at this time (refer to figure 7-11 ). figure 7-10. operation with cm4 at 1 to ffffh remark interval time = (n + 1) x count clock cycle n = 1 to 65535 (ffffh) count clock count up tm4 clear tm4 cm4 coincidence detection (intcm4) clear n01 n
136 chapter 7 timer/counter function (real-time pulse unit) figure 7-11. when cm4 is set to 0 remark interval time = (ffffh + 2) x count clock cycle count clock count up tm4 clear tm4 cm4 coincidence detected (intcm4) overflow ffffh 0 0 1 0 clear
137 chapter 7 timer/counter function (real-time pulse unit) 7.6 application examples (1) operation as interval timer (timer 4) timer 4 is used as an interval timer that repeatedly generates an interrupt request at time intervals specified by the count value set in advance to compare register cm4. figure 7-12 shows the timing. figure 7-13 illustrates the setting procedure. figure 7-12. example of timing of interval timer operation (timer 4) remark n: value of cm4 register t: interval time = (n + 1) x count clock cycle figure 7-13. setting procedure of interval timer operation (timer 4) interval timer setting of tmc4 register sets count value to cm4 register cm4 <- n count starts tmc4. ce4 <- 1 ; specifies count clock ; sets ce4 bit to 1 intcm4 interrupt tm4 count value 0 compare register (cm4) interrupt request (intcm4) n count starts clear clear t
138 chapter 7 timer/counter function (real-time pulse unit) (2) pulse width measurement (timer 1) timer 1 is used to measure pulse width. in this example, the width of the high or low level of an external pulse input to the intp12 pin is measured. the value of timer 1 (tm1) is captured to a capture/compare register (cc12) in synchronization with the valid edge of the intp12 pin (both the rising and falling edges), as shown in figure 7-14. to calculate the pulse width, the difference between the count value of tm1 captured to the cc12 register on detection of valid edge n (dn), and the count value on detection of valid edge (nC1) (dnC1) is calculated. this difference is multiplied by the count clock. figure 7-15 shows the setting procedure. figure 7-14. pulse width measurement timing (timer 1) remark dn: count value of tm1 (n = 0, 1, 2, ...) ffffh d0 d1 d3 d2 tm1 count value 0 external pulse input (intp12) capture/compare register (cc12) capture capture capture capture d3 d2 d1 d0 t1 t2 t3 t1 = (d1?0) x count clock cycle t2 = {(10000h?1) + d2} x count clock cycle t3 = (d3?2) x count clock cycle
139 chapter 7 timer/counter function (real-time pulse unit) figure 7-15. setting procedure for pulse width measurement (timer 1) figure 7-16. interrupt request processing routine calculating pulse width (timer 1) caution if an overflow occurs two times or more between (nC1)th capture and nth capture, the pulse width cannot be measured. intpn (both rising and falling edges) calculation of pulse width yn = cc12? n? tn = yn x count clock cycle stores nth capture data to buffer memory xn <- cc12 reti ; xn, yn : variable ; tn : pulse width setting of tmc1 register setting of intm2 register intm2. es121 <- 1 intm2. es120 <- 1 setting of tum1 register tum1. cms12 <- 0 initialization of buffer memory for capture data storage x0 <- 0 count starts tmc1. ce1 <- 1 enables interrupt intp12 interrupt ; specifies count clock ; specifies both edges as valid edge of intp12 input signal ; sets capture register ; sets ce1 bit to 1 pulse width measurenent
140 chapter 7 timer/counter function (real-time pulse unit) (3) pwm output (timer 1) any square wave can be output to timer output pins (to10 and to11) by combining the use of timer 1 and the timer output function. (a) using timer 1 two capture/compare registers, cc10 and cc11, are used in this example of pwm output. a pwm signal with an accuracy of 16 bits can be output from the to10 pin. figure 7-17 shows the timing. when timer 1 is used as a 16-bit timer, the rising timing of the pwm output is determined by the value set to capture/compare register cc10, and the falling timing is determined by the value set to capture/ compare register cc11. figure 7-18 shows the programming procedure at this time. figure 7-17. pwm output timing (tm1) remark dxx: set value of compare register t1 = {(10000hCd00) + d01} x count clock cycle t2 = {(10000hCd10) + d11} x count clock cycle ffffh ffffh ffffh cc10 cc11 cc11 cc10 cc10 tm1 count value 0 coincidence coincidence coincidence coincidence coincidence capture/compare register (cc10) interrupt request (intcc10) capture/compare register (cc11) interrupt request (intcc11) timer output (to10 pin) d00 d01 d12 t1 t2 d02 d10 d11
141 chapter 7 timer/counter function (real-time pulse unit) figure 7-18. programming procedure of pwm output (timer 1) pwm output setting of toc1 register toc1. ento10 <- 1 toc1. alv10 <- 1 setting of tum1 register tum1. cms10 <- 1 tum1. cms11 <- 1 specifies p00 pin as timer output pin to10 by pmc0 register pmc0. pmc00 <- 1 setting of tmc1 register sets count value to cc10 register cc10 <- d00 enables interrupt count starts tmc1. ce <- 1 sets count value to cc11 register cc11 <- d10 ; specifies active level (high level) enables timer ouput ; specifies operation of cc10 and cc11 registers (specifies compare operation) ; sets ce1 bit to 1 ; specifies count clock of tm1 intcc10 interrupt intcc11 interrupt
142 chapter 7 timer/counter function (real-time pulse unit) figure 7-19. interrupt request processing routine, modifying compare value (timer 1) intcc10 sets time (number of counts) to reset (0) to10 output next, to compare register cc11 reti intcc11 sets time (number of counts) to set (1) to10 output next, to compare register cc10 reti
143 chapter 7 timer/counter function (real-time pulse unit) (4) cycle measurement (timer 1) timer 1 can be used to measure the cycle or frequency of an external pulse input to the intpn pin (n = 10 to 13). in this example, the cycle of the external pulse input to the intp10 pin is measured with a resolution of 16 bits, by combining the use of timer 1 and the capture/compare register cc10. the valid edge of the intp10 input signal is specified by the intm2 register to be the rising edge. to calculate the cycle, the difference between the count value of tm1 captured to the cc10 register at the nth rising edge (dn), and the count value captured at the (nC1)th rising edge (dnC1), is calculated, and the value multiplied by the count clock frequency. figure 7-21 shows the setting procedure at this time. figure 7-20. cycle measurement timing (tm1) remark dn: count value of tm1 (n = 0, 1, 2, ...) ffffh ffffh ffffh tm1 count value 0 interrupt request (intp10) capture/compare register (cc10) d0 d1 d2 t1 t2 d2 d1 d0 t1 = {(10000h?0) + d1} x count clock cycle t2 = {(10000h?1) + d2} x count clock c y cle
144 chapter 7 timer/counter function (real-time pulse unit) figure 7-21. set-up procedure for cycle measurement (timer 1) figure 7-22. interrupt request processing routine calculating cycle (timer 1) setting of tmc1 register setting of tum1 register tum1. cms10 <- 1 setting of intm2 register intm2. es101 <- 0 intm2. es100 <- 1 initialization of buffer memory for capture data storage x0 <- 0 count starts tmc1. ce1 <- 1 enables interrupt intp10 interrupt ; specifies count clock ; specifies cc10 register as compare register ; specifies rising edge as valid edge of intp10 signal ; sets ce1 bit to 1 cycle measurement intp10 interrupt calculation of cycle yn = cc10? n? tn = yn x count clock cycle stores nth capture data to buffer memory xn <- cc10 reti ; tn : cycle
145 chapter 7 timer/counter function (real-time pulse unit) 7.7 note coincidence is detected by the compare register immediately after the timer value matches the compare register value, and does not take place in the following cases: (1) when compare register is rewritten (tm1, tm4) (2) when timer is cleared by external input (tm1) (3) when timer is cleared (tm4) count clock value of timer compare register value coincidence detection n? n n + 1 m writing to register coincidence does not occur coincidence does not occur l n value of timer external clear input coincidence detection count clock compare register value n? n 0 1 0000h coincidence does not occur l count clock value of timer internal coincidence clear coincidence detection fffeh ffffh 0 0 1 coincidence does not occur
146 chapter 7 timer/counter function (real-time pulse unit) when timer 1 is used as a free-running timer, the timer value is cleared to 0 when the timer overflows. count clock value of timer overflow interrupt fffeh ffffh 0 1 2 3
147 chapter 8 serial interface function chapter 8 serial interface function 8.1 features the v852 is provided with four transmission/reception channels for the serial interface function. there are the following two types of interfaces, and each of them functions independently. (1) asynchronous serial interface (uart): 1 channel (2) clocked serial interface (csin): 3 channels (n = 0 to 2) the uart transmits/receives 1-byte serial data following a start bit and can perform full-duplex communication. the csi uses three signal lines to transfer data (3-wire serial i/o): the serial clock (sckn) (n = 0 to 2), serial input (sin) (n = 0 to 2), and serial output (son) (n = 0 to 2) lines.
148 chapter 8 serial interface function 8.2 asynchronous serial interface (uart) 8.2.1 features transfer rate: 110 bps to 38400 bps (with baud rate generator, at f = 25 mhz) 781 kbps max. (with f /2, at f = 25 mhz) full-duplex communication two-pin configuration: txd: transmit data output pin rxd: receive data input pin receive error detection function ? parity error ? framing error ? overrun error three interrupt sources ? receive error interrupt (intser0) ? reception completion interrupt (intsr0) ? transmission completion interrupt (intst0) character length of transmit/receive data is specified by asim00 and asim01 registers. character length: 7, 8 bits 9 bits (when extended) parity function: odd, even, 0, none transmit stop bit: 1, 2 bits internal baud rate generator
149 chapter 8 serial interface function 8.2.2 configuration of asynchronous serial interface the asynchronous serial interface is controlled by asynchronous serial interface mode register (asim) and asynchronous serial interface status register (asis). the receive data is stored in the receive buffer (rxb), and the transmit data is written to the transmit shift register (txs). figure 8-1 shows the configuration of the asynchronous serial interface. (1) asynchronous serial interface mode registers (asim00, asim01) asim00 and asim01 are 8-bit registers that specify the operation of the asynchronous serial interface. (2) asynchronous serial interface status register (asis0) asis0 is a register containing flags that indicate receive errors, if any, and a transmit status flag. each receive error flag is set to 1 when a receive error occurs, and is reset to 0 when data is read from the receive buffer (rxb0, rxb0l), or when new data is received (if the next data contains an error, the corresponding error flag is set). the transmit status flag is set to 1 when transmission is started, and reset to 0 when transmission ends. (3) reception control parity check the reception operation is controlled according to the contents programmed in the asim00 and asim01 registers. during the receive operation, errors such as parity error are also checked. if an error is found, the appropriate value is set to the asis0 register. (4) receive shift register this shift register converts the serial data received on the rxd pin into parallel data. when it receives 1 byte of data, it transfers the receive data to the receive buffer. the receive shift register cannot be accessed by the cpu. (5) receive buffer (rxb0, rxb0l) rxb0 is a 9-bit buffer register that holds receive data. if data of 7 or 8 bits/character is received, 0 is stored to the most significant bit position of this register. if this register is accessed in 16-bit units, rxb0 is specified. to access in lower 8-bit units, rxb0l is specified. while reception is enabled, the receive data is transferred from the receive shift register to the receive buffer in synchronization with shift-in processing of 1 frame. when the data is transferred to the receive buffer, a reception completion interrupt request (intsr0) occurs. (6) transmit shift register (txs0, txs0l) txs0 is a 9-bit shift register used for transmit operation. when data is written to this register, the transmission operation is started. a transmission complete interrupt request (intst0) is generated after each complete data frame is trasmitted. when this register is accessed in 16-bit units, txs0 is specified. to access in lower 8-bit units, txs0l is specified. (7) transmission parity control a start bit, parity bit, and stop bit are appended to the data written to the txs0 register, according to the contents programmed in the asim00 and asim01 registers, to control the transmission operation.
150 chapter 8 serial interface function (8) selector selects the source of the serial clock. figure 8-1. block diagram of asynchronous serial interface internal bus 16/8 8 receive buffer receive shift register receive control parity check 1 16 1 16 1 2 intst0 intsr0 intser0 transmission parity control selector f baud rate generator 88 16/8 asis0 pe0 fe0 ove0 sot0 rxe0 ps01 ps00 cl0 sl0 sols0 ebs0 asim00 asim01 rxb0 rxb0l txs0 txs0l transmit shift register
151 chapter 8 serial interface function 8.2.3 mode registers and control registers (1) asynchronous serial interface mode registers (asim00 and asim01) these registers specify the transfer mode of the uart. they can be read/written in 8- or 1-bit units. bit position bit name funciton 6 rxe0 receive enable enables/disables reception. 0: disables reception 1: enables reception when reception is disabled, the receive shift register does not detect the start bit. data is not shifted into the receive shift register and neither is any transfer to the receive buffer performed. therefore, the previous contents of receive buffer are retained. when reception is enabled, the data is shifted into the receive shift register and transferred to the receive buffer when one complete frame has been received. a reception completion interrupt (intsr0) is generated in synchronization with the transfer to the receive buffer. 7 1 6 rxe0 5 ps01 4 ps00 3 cl0 2 sl0 1 0 0 scls0 asim00 address fffff0c0h at reset 80h
152 chapter 8 serial interface function bit position bit name function 5, 4 ps01, ps00 parity select specifies parity bit. ps01 ps00 operation 0 0 no parity. extended bit operation 0 1 0 parity transmission side -> transmits with parity bit 0 reception side -> does not generate parity error on reception 1 0 odd parity 1 1 even parity ? even parity parity bit is set to 1 when number of bits equal to one in received data is odd. if number of bits that are one is even, parity bit is cleared to 0. in this way, number of bits that are 1 in transmit data and parity bit is controlled to become even. during reception, number of bits that are 1 in receive data and parity bit are counted. if it is odd, parity error occurs. ? odd parity in contrast to even parity, number of bits included in transmit data and parity bit that are 1 is controlled to become odd. during reception, parity error occurs if the number of 1s in the receive data and parity bit are added up to become even. ? 0 parity parity bit is cleared to 0 during transmission, regardless of transmit data. during reception, the parity bit is not checked. therefore, parity error does not occur regardless of whether parity bit is 0 or 1. ? no parity no parity bit is appended to the transmit data. reception is performed on assumption that there is no parity bit. because no parity bit is used, parity error does not occur. extended bit operation can be specified by ebs0 bit of asim01 register. 3 cl0 character length specifies character length of one frame. 0: 7 bits 1: 8 bits 2 sl0 stop bit length specifies stop bit. 0: 1 bit 1: 2 bits
153 chapter 8 serial interface function bit position bit name function 0 scls0 serial clock source specifies serial clock. 0: specified by baud rate generator and bprm0 (baud rate generator prescaler mode register) 1: f /2 ? when scls0 = 1 f /2 (system clock) is selected as serial clock source. in asynchronous mode, baud rate is expressed as follows because sampling rate of x16 is used: baud rate = bps value of baud rate when typical clock is used based on above expression is as follows: f 25 mhz 20 mhz 16 mhz 12.5 mhz 10 mhz 8 mhz 5 mhz baud rate 781 k 625 k 500 k 390 k 312 k 250 k 156 k ? when scls0 = 0 baud rate generator output is selected as serial clock source. for details of baud rate generator, refer to 8.4 baud rate generator (brg) . caution the operation of uart is not guaranteed if the bits 0 to 6 of this register are changed while uart is transmitting/receiving data. bit position bit name function 0 ebs0 extended bit select specifies extended bit operation of transmit/receive data when no parity is specified (ps01, ps00 = 00). 0: disables extended bit operation 1: enables extended bit operation when extended bit operation is enabled, 1 data bit is appended as most significant bit to 8-bit transmit/receive data, and therefore 9-bit data is communicated. extended bit operation is valid only when no parity is specified by asim00 register. if zero, even, or odd parity is specified, specification by ebs0 bit is invalid, and extended bit is not appended. f /2 16 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 ebs0 asim01 address fffff0c2h at reset 00h
154 chapter 8 serial interface function (2) asynchronous serial interface status register 0 (asis0) this register contains three error flags that indicate the receive error status for each character received and the status of the transmit shift register. the error flags always indicate the status of an error that has occurred most recently. if two or more errors occur before the current received data, only the status of the error that has occurred last is retained. if a receive error occurs, read the receive buffer rxb0 or rxb0l after reading the asis0 register, and then clear the error flag. this register can only be read in 8- or 1-bit units. bit position bit name function 7 sot0 status of transmission status flag that indicates transmission operation status. set (1) : beginning of transmission of a data frame (writing to txs register) clear (0): end of transmission of a data frame (occurrence of intst0) when serial data transfer begins, this flag will indicate if the transmit shift register is ready to be written or not. 2 pe0 parity error status flag that indicates parity error. set (1) : transmit parity and receive parity do not match clear (0): the data is read from the receive buffer. 1 fe0 framing error status flag that indicates framing error. set (1) : stop bit is not detected clear (0): the data is read from the receive buffer. 0 ove0 overrun error status flag that indicates overrun error. set (1) : the uart completes the next receive process before taking the receive data from the receive buffer. clear (0): the data is read from the receive buffer. because contents of receive shift register are transferred to receive buffer each time one frame of data has been received, if overrun error occurs, next receive data is written over contents of receive buffer, and previous receive data is discarded. 7 sot0 6 0 5 0 4 0 3 0 2 pe0 1 fe0 0 ove0 asis0 address fffff0c4h at reset 00h
155 chapter 8 serial interface function (3) receive buffers (rxb0 and rxb0l) rxb0 is a 9-bit buffer register that holds the receive data. when 7- or 8-bit/character is received, the higher bit of this register is 0. when this register is accessed in 16-bit units, rxb0 is specified. to access in lower 8-bit units, rxb0l is specified. when reception is enabled, the receive data is transferred from the receive shift register to the receive buffer when one complete frame of data (or character) has been received. when the receive data is transferred to the receive buffer, a reception completion interrupt request (intsr0) occurs. when reception is disabled, the data is not shifted into the receive shift register and the reception completion interrupt is not generated. the previous contents of the receive buffer are retained. rxb0 enables 16-bit read access only, and rxb0l enables 8-/1-bit read access only. bit position bit name function 8 rxeb0 receive extended buffer extended bit when 9-bit/character is received. this bit is cleared to zero when 7- or 8-bit/character is received. 7 to 0 rxb0n receive buffer (n = 7 to 0) these bits store receive data. the rxb07 bit is cleared to zero when 7-bit/character is received. 76 0 5 0 43210 rxb00 rxb0 address fffff0c8h at reset undefined rxb01 rxb02 rxb03 rxb04 rxb05 rxb06 rxb07 rxb0 0 0 0 0 0 12 11 10 9 8 15 14 13 76543210 rxb00 rxb01 rxb02 rxb03 rxb04 rxb05 rxb06 rxb07 rxb0l address fffff0cah at reset undefined
156 chapter 8 serial interface function (4) transmit shift registers (txs0, txs0l) txs0 is a 9-bit shift register for data transmission. the transmit operation is started when data is written to this register. transmission complete interrupt request (intst0) is generated after each complete data frame is transmitted. when this register is accessed in 16-bit units, txs0 is specified. to access in lower 8-bit units, txs0l is specified. txs0 enables 16-bit write access only, and txs0l enables 8-bit write access only. bit position bit name function 8 txed0 transmit extended data extended bit on transmission of 9-bit/character 7 to 0 txs0n transmit shifter (n = 7 to 0) writes transmit data. caution as the uart of the v852 does not have a transmit buffer, an interrupt request synchronizing with the completion of the transmission of one frame of data is generated instead of the interrupt request generated at the end of transmission (completion of transfer to buffer). 76 0 5 0 43210 txs00 txs0 address fffff0cch at reset undefined txs01 txs02 txs03 txs04 txs05 txs06 txs07 txed0 0 0 0 0 0 12 11 10 9 8 15 14 13 76543210 txs0l address fffff0ceh at reset undefined txs00 txs01 txs02 txs03 txs04 txs05 txs06 txs07
157 chapter 8 serial interface function 8.2.4 interrupt request uart generates the following three types of interrupt requests: ? receive error interrupt ? reception completion interrupt ? transmission completion interrupt of these three, the receive error interrupt has the highest default priority, followed by the reception completion interrupt and transmission completion interrupt. table 8-1. default priority of interrupts interrupt priority receive error 1 reception completion 2 transmission completion 3 (1) receive error interrupt (intser0) a receive error interrupt occurs as a result of oring the three types of receive errors described in description of the asis0 register when reception is enabled. this interrupt does not occur when reception is disabled. (2) reception completion interrupt (intsr0) the reception completion interrupt occurs if data is received in the receive shift register and then transferred to the receive buffer when reception is enabled. this interrupt also occurs when a receive error occurs, but the receive error interrupt has the higher priority. the reception completion interrupt does not occur when reception is disabled. (3) transmission completion interrupt (intst0) because the uart of the v852 does not have a transmit buffer, a transmission completion interrupt occurs when one frame of transmit data containing a 7-/8-/9-bit character is shifted out from the transmit shift register. the transmission completion interrupt is output when the last bit of data has been transmitted.
158 chapter 8 serial interface function 8.2.5 operation (1) data format full-duplex serial data is transmitted/received. one data frame of the transmit/receive data consists of a start bit, character bits, parity bit, and stop bit, as shown in figure 8-2. the length of the character bit, parity, and the length of the stop bit in one data frame are specified by the asynchronous serial interface mode registers (asim00 and asim01). figure 8-2. format of transmit/receive data of asynchronous serial interface ? start bit ............................ 1 bit ? character bit ................... 7/8/9 bits (with extended bit) ? parity/expansion bit ........ even/odd/0/none/expansion bit ? stop bit ............................ 1/2 bits (2) transmission transmission is started when data is written to the transmit shift register (txs0 or txs0l). the next data is written to the txs0 or txs0l register by the processing routine of the transmission completion interrupt (intst0). (a) transmission enabled status the uart of the v852 is always enabled to transmit data. because the v852 does not have a pin that inputs a transmit enable signal, a general input port is used when it is necessary to check whether the other party is ready to receive data. (b) starting transmission transmission is started by writing data to the transmit shift register (txs0, txs0l). the transmit data is transferred starting from the start bit with the lsb first. the start bit, parity/expansion bit, and stop bit are automatically appended. d0 d1 d2 d3 d4 d5 d6 d7 parity/ expansion bit stop bit start bit character bit 1 data frame
159 chapter 8 serial interface function (c) transmission interrupt request when one frame of data or character has been completely transferred, a transmission completion interrupt request (intst0) occurs. unless the data to be transmitted next is written to the txs0 or txs0l register, the transmit operation is aborted. the communication rate drops unless the next transmit data is written to the txs0 or txs0l register immediately after transmission has been completed. cautions 1. the transmission completion interrupt request (intst0) is generated after each complete data frame is transmitted out of the transmit shift register. it is not generated by the empty state of txs0 or txs0l. because of this, the intst0 interrupt will not be generated immediately after reset. 2. during the transmit operation, writing data into the txs0 or txs0l register is ignored (the data is discarded) until intst0 is generated. figure 8-3. asynchronous serial interface transmission completion interrupt timing (a) stop bit length: 1 (b) stop bit length: 2 txd (output) intst0 start d0 d1 d2 d6 d7 parity/ expansion parity/ expansion stop d0 d1 d2 d6 d7 stop start txd (output) intst0
160 chapter 8 serial interface function (3) reception when reception is enabled, sampling of the rxd pin is started, and reception of data begins when the start bit is detected. each time one frame of data or character has been received, the reception completion interrupt (intsr0) occurs. usually, the receive data is transferred from the receive buffer (rxb0, rxb0l) to memory by this interrupt processing. (a) reception enabled status reception is enabled when the rxe0 bit of the asim00 register is set to 1. rxe0 = 1: reception is enabled rxe0 = 0: reception is disabled when reception is disabled, the receive hardware stands by in the initial status. at this time, the reception completion interrupt/receive error interrupt does not occur, and the contents of the receive buffer are retained. (b) starting reception reception is started when the start bit is detected. the rxd pin is sampled with the serial clock specified by the asim00 register. the rxd pin is sampled again eight clocks after the falling edge of the rxd pin has been detected. if the rxd pin is low at this time, it is recognized as the start bit, and reception is started. after that, the rxd pin is sampled in 16 clock ticks. if the rxd pin is high eight clocks after the falling edge of the rxd pin has been detected, this falling edge is not recognized as the start bit. the serial clock counter is reinitialized, and the uart waits for the input of the next falling edge or valid start bit. (c) reception completion interrupt request when one frame of data has been received with rxe0 = 1, the receive data in the shift register is transferred to rxb0, and a reception completion interrupt request (intsr0) is generated. if an error occurs, the receive data that contains an error is transferred to the receive buffer (rxb0, rxb0l), and the transmission completion interrupt (intsr0) and receive error interrupt (intser0) occur simultaneously. when the rxe0 bit is reset to 0 during reception, the receive operation is immediately disabled. the contents of the receive buffer (rxb0, rxb0l) and asynchronous serial interface status register (asis0) are not changed, and the reception completion interrupt (intsr0) and receive error interrupt (intser0) will not be generated.
161 chapter 8 serial interface function figure 8-4. asynchronous serial interface reception completion interrupt timing (d) reception error flag three error flags, parity error, framing error, and overrun error flags, are related with the reception operation. the receive error interrupt request occurs as a result of oring these three error flags. by reading the contents of the asis0 register, the error which caused the receive error interrupt (intser0) can be identified. the contents of the asis0 register are reset to 0 when the receive buffer (rxb0, rxb0l) is read or the next data frame is received (if the next data contains an error, the corresponding error flag is set). receive error cause parity error parity specified during transmission does not coincide with parity of receive data framing error stop bit is not detected overrun error next data is completely received before data is read from receive buffer figure 8-5. receive error timing rxd (input) intsr0 start d0 d1 d2 d6 d7 stop parity/ expansion rxd (input) intsr0 start d0 d1 d2 d6 d7 stop intser0 parity/ expansion
162 chapter 8 serial interface function 8.3 clocked serial interface 0 to 2 (csi0 to csi2) 8.3.1 features number of channels: 3 channels (csin) (n = 0 to 2) high transfer speed: 6.25 mbps max. (with f /2, at f = 25 mhz) half duplex communication character length: 8 bits msb first/lsb first selectable external serial clock input/internal serial clock output selectable 3 lines: son : serial data output (n = 0 to 2) sin : serial data input (n = 0 to 2) sckn: serial clock i/o (n = 0 to 2) interrupt source: 3 ? interrupt request signal (intcsin) (n = 0 to 2) the csin is controlled by the clocked serial interface mode register (csimn) (n = 0 to 2). the transmit/receive data is read/written from/to the serial i/o shift register (sion) (n = 0 to 2). (1) clocked serial interface mode register (csimn) csimn is an 8-bit register that specifies the operation of the clocked serial interface. (2) serial i/o shift register (sion) sion is an 8-bit register that converts serial data into parallel data, and vice versa. sion is used for both transmission and reception. data is shifted in (received) or shifted out (transmitted) from the msb or lsb side. the actual transmitting and receiving of data is actually performed by writing data to and reading data from the sion. (3) serial clock selector selects the serial clock to be used. (4) serial clock control circuit controls supply of the serial clock to the sion. when the internal clock is used, it also controls the clock output to the sckn (n = 0 to 2) pin. (5) serial clock counter counts the serial clocks being output and the serial clocks received during transmission/reception to check whether 8-bit data has been transmitted or received. (6) interrupt signal generation control circuit controls whether an interrupt request is generated when the serial clock counter has counted eight serial clocks.
163 chapter 8 serial interface function 8.3.2 configuration ctxe0 crxe0 csot0 mod0 cls01 cls00 csim0 si0 so0 sck0 serial i/o shift register (sio0) so latch dq 2 1 serial clock control circuit serial clock counter interrupt control circuit intcsi0 internal bus selector baud rate generator /2 csi0 csi1 si1 so1 sck1 csi2 si2 so2 sck2 selector f f
164 chapter 8 serial interface function 8.3.3 mode registers and control registers (1) clocked serial interface mode register n (csimn) (n = 0 to 2) this register specifies the basic operation mode of csin. it can be read/written in 8- or 1-bit units (note, however, that bit 5 can only be read). bit position bit name function 7 ctxen csi transmit enable enables or disables transmission. 0: disables transmission 1: enables transmission when ctxen = 0, output buffers of both so and si pins go into high-impedance state. 6 crxen csi receive enable disables or enables reception. 0: disables reception 1: enables reception if serial clock is received when transmission enabled (ctxen = 1) and reception are disabled, 0 is input to sion. when reception is disabled (crxen = 0) during reception, the contents of sion become undefined. 5 csotn csi status of transmission indicates that transfer operation is in progress. set (1): transfer start timing (writing to sio0 register) clear (0): transfer end timing (intcsi occurs) this bit is used to check whether writing to sion is permitted or not. serial data transfer is started by enabling transmission (ctxen = 1). 2 modn mode specifies first bit. 0: msb first 1: lsb first 1, 0 clsn1, clsn0 clock source specifies serial clock. clsn1 clsn0 specifies serial clock sckn pin 0 0 external clock input 0 1 internal clock specified by bprmm register note1 output 10 f /4 note2 output 11 f /2 note2 output notes 1. for setting of bprmm (m = 0, 1) register, refer to section 8.4 baud rate generator (brg) . 2. f /4 and f /2 indicate divider signal ( f = system clock). remark n = 0 to 2 address fffff088h 7 ctxe0 csim0 6 crxe0 5 csot0 4 0 3 0 2 mod0 1 cls01 0 cls00 at reset 00h address fffff098h 7 ctxe1 csim1 6 crxe1 5 csot1 4 0 3 0 2 mod1 1 cls11 0 cls10 at reset 00h address fffff0a8h 7 ctxe2 csim2 6 crxe2 5 csot2 4 0 3 0 2 mod2 1 cls21 0 cls20 at reset 00h
165 chapter 8 serial interface function (2) serial i/o shift register n (sion) (n = 0 to 2) this register converts 8-bit serial data into parallel data, and vice versa. the actual transmitting and receiving of data is performed by writing data to and reading data from the sion. a shift operation of sion is performed when ctxen (n = 0 to 2) = 1 or crxen (n = 0 to 2) = 1. this register can be read/written in 8- or 1-bit units. bit position bit name function 7 to 0 sionm serial i/o data is shifted in (received) or out (transmitted) from msb or lsb side. remark n = 0 to 2, m = 0 to 7 address fffff08ah 7 sio07 sio0 6 sio06 5 sio05 4 sio04 3 sio03 2 sio02 1 sio01 0 sio00 at reset undefined address fffff09ah 7 sio17 sio1 6 sio16 5 sio15 4 sio14 3 sio13 2 sio12 1 sio11 0 sio10 at reset undefined address fffff0aah 7 sio27 sio2 6 sio26 5 sio25 4 sio24 3 sio23 2 sio22 1 sio21 0 sio20 at reset undefined
166 chapter 8 serial interface function 8.3.4 basic operation (1) transfer format the csin (n = 0 to 2) of the v852 performs interfacing by using three lines: one clock line and two data lines. serial transfer is started by executing an instruction that writes transfer data to the sion (n = 0 to 2) register. during transmission, the data is output from the son (n = 0 to 2) pin in synchronization with the falling edge of sckn (n = 0 to 2). during reception, the data input to the sin (n = 0 to 2) pin is latched in synchronization with the rising edge of sckn (n = 0 to 2). sckn stops when the serial clock counter overflows (at the rising of the 8th count), and sckn remains high until the next data transmission or reception is started. at the same time, an interrupt request signal intcsin (n = 0 to 2) is generated. caution if ctxen (n = 0 to 2) is changed from 0 to 1 after the transmit data is sent to the sion register, serial transfer will not begin. remark n = 0 to 2 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 input data latched 12345678 sckn sin son csotn flag intcsin transfer starts in synchronization with falling of sckn execution of sion write instruction serial transmission/ reception completion interrupt occurs
167 chapter 8 serial interface function (2) enabling transmission/reception the csin (n = 0 to 2) of the v852 has only one 8-bit shift register and does not have a buffer. transmission and reception are therefore performed simultaneously. (a) transmission/reception enabling condition the csin transmission/reception enabling conditions are specified using the ctxen (n = 0 to 2) and crxen (n = 0 to 2) bits of the csimn (n = 0 to 2) register. ctxen crxen transmission/reception 0 0 disables transmission/reception 0 1 enables reception 1 0 enables transmission 1 1 enables transmission/reception remark n = 0 to 2 (i) disabling sion output by ctxen when ctxen = 0, the son pin output of csin goes into a high-impedance state. when ctxen = 1, the data of the sion register of csin is output. (ii) disabling sion input by crxen when crxen = 0, the sion register input of csin is 0. when crxen = 1, the sin pin input of csin is input to the shift register. (iii) to check transmit data to receive the transmit data and to check whether bus contention occurs, set ctxen and crxen to 1. (b) starting transmission/reception transmission/reception is started by reading/writing the sion register. transmission/reception is controlled by setting the transmission enable bit (ctxen) and reception enable bit (crxen) as follows: ctxen crxen start condition 0 0 does not start 0 1 reads from sion 1 0 writes to sion 1 1 writes to sion 0 0 -> 1 rewrites crxen bit remark n = 0 to 2 if ctxen bit is not changed from 0 to 1 before reading data from or writing data to the sion register, transfer will not begin. the bottom of the table means that, if the crxen bit is changed from 0 to 1 when the ctxen bit is 0, the serial clock will be generated to initiate receive operation of csin.
168 chapter 8 serial interface function 8.3.5 transmission in 3-wire serial i/o mode transmission is started when data is written to the sion (n = 0 to 2) register after transmission has been enabled by the csimn (n = 0 to 2) register. (1) starting transmission transmission is started by writing the transmit data to the sion register after the ctxen (n = 0 to 2) bit of the csimn register has been set (the crxen (n = 0 to 2) bit is cleared to 0). if the ctxen bit is reset to 0, the son (n = 0 to 2) pin goes into a high-impedance state. (2) transmitting data in synchronization with serial clock (a) when internal clock is selected as serial clock when transmission is started, the serial clock is output from the sckn (n = 0 to 2) pin, and at the same time, data is sequentially output to the son pin from sion register in synchronization with the falling edge of the serial clock. (b) when external clock is selected as serial clock when transmission is started, the data is sequentially output from the sion register to the son pin in synchronization with the falling of the serial clock input to the sckn pin immediately after transmission has been started. the shift operation is not performed even if the serial clock is input to the sckn pin if transmission is not enabled, and the output level of the son pin will not change. figure 8-6. timing of 3-wire serial i/o mode (transmission) remark n = 0 to 2 do7 do6 do5 do4 do3 do2 do1 do0 12345678 sckn sin son intcsin transfer starts in synchronization with falling of sckn execution of sion write instruction serial transmission/ reception completion interrupt occurs
169 chapter 8 serial interface function 8.3.6 reception in 3-wire serial i/o mode reception is started if the status is changed from reception disabled to reception enabled status by the csimn (n = 0 to 2) register or if the sion (n = 0 to 2) register is read by the cpu with reception enabled. (1) starting reception reception can be started in the following two ways: <1> changing the status of the crxen (n = 0 to 2) bit of the csimn register from 0 (reception disabled) to 1 (reception enabled) <2> reading the receive data from the sion when the crxe0 bit of the csimn register is 1 (reception enabled) if crxen has already been set to 1, writing 1 to this bit does not initiate receive operation. when crxen = 0, the input to sion register is 0. (2) receiving data in synchronization with serial clock (a) when internal clock is selected as serial clock when reception is started, the serial clock is output from the sckn (n = 0 to 2) pin, and at the same time, data is sequentially loaded from the sin (n = 0 to 2) pin to the sion register in synchronization with the rising edge of the serial clock. (b) when external clock is selected as serial clock when reception is started, the data is sequentially loaded from the sin (n = 0 to 2) pin to sion in synchronization with the rising of the serial clock input to the sckn pin immediately after reception has been started. the shift operation is not performed even if the serial clock is input to the sckn pin when reception is not enabled. figure 8-7. timing of 3-wire serial i/o mode (reception) remark n = 0 to 2 di7 di6 di5 di4 di3 di2 di1 di0 12345678 sckn sin son intcsin transfer starts in synchronization with falling edge of sckn execution of sion write instruction serial transmission/ reception completion interrupt occurs
170 chapter 8 serial interface function 8.3.7 transmission/reception in 3-wire serial i/o mode transmission and reception can be executed simultaneously if both transmission and reception are enabled by the csimn (n = 0 to 2) register. (1) starting transmission/reception transmission and reception can be performed simultaneously (transmission/reception operation) when both the ctxen (n = 0 to 2) and crxen (n = 0 to 2) bits of the csimn register are set to 1. transmission/reception can be started by writing the transmit data to the sion (n = 0 to 2) register when both the ctxen and crxen bits of the csimn register are 1 (transmission/reception enabled). if crxen has already been set to 1, writing 1 to this bit does not initiate transmit/receive operation. (2) transmitting data in synchronization with serial clock (a) when internal clock is selected as serial clock when transmission/reception is started, the serial clock is output from the sckn (n = 0 to 2) pin, and at the same time, data is sequentially set to the son (n = 0 to 2) pin from the sion register in synchronization with the falling edge of the serial clock. simultaneously, the data of the sin (n = 0 to 2) pin is sequentially loaded to sion register in synchronization with the rising edge of the serial clock. (b) when external clock is selected as serial clock when transmission/reception is started, the data is sequentially output from the sion register to the son pin in synchronization with the falling edge of the serial clock input to the sckn pin immediately after transmission/reception has been started. the data of the sin pin is sequentially loaded to the sion register in synchronization with the rising edge of the serial clock. the shift operation is not performed even if the serial clock is input to the sckn pin when transmission/reception is not enabled, and the output level of the son pin does not change.
171 chapter 8 serial interface function figure 8-8. timing of 3-wire serial i/o mode (transmission/reception) remark n = 0 to 2 8.3.8 system configuration example data 8 bits long is transferred by using three signal lines: serial clock (sckn) (n = 0 to 2), serial input (sin) (n = 0 to 2), and serial output (son) (n = 0 to 2). this feature is effective for connecting peripheral i/os and display controllers that have a conventional clocked serial interface. to connect two or more devices, a handshake line is necessary. various devices can be connected, because it can be specified whether the data is transmitted starting from the msb or lsb. figure 8-9. example of csi system configuration remark n = 0 to 2 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 12345678 sckn sin son intcsin transfer starts in synchronization with falling of sckn execution of sion write instruction serial transmission/ reception completion interrupt occurs (3-wire serial l/o 3-wire serial i/o) master cpu sckn son sin port (interrupt) port sckn sin son port interrupt (port) slave cpu handshake line
172 chapter 8 serial interface function 8.4 baud rate generator 0, 1 (brg0, brg1) 8.4.1 configuration and function the serial interface can use the output of the internal baud rate generator or f (system clock) as the serial clock. the serial clock source for the uart is specified by the scls0 bit of the asim00 register. the serial clock source for the csin (n = 0 to 2) is specified by the clsn0 and clsn1 bits of the csimn (n = 0 to 2) register. when the output of the baud rate generator is specified, the baud rate generator will be used as the clock source. because the serial clock for transmission/reception is shared by both the transmission and reception portions, the same baud rate is used for both transmission and reception. figure 8-10. block diagram of baud rate generator baud rate generator 0 bprm0 brg0 comparison match clear tmbrg0 uart csi0 prescaler brce0 bpr02 bpr01 bpr00 2 1 baud rate generator 1 bprm1 brg1 comparison match clear tmbrg1 csi1 csi2 prescaler brce1 bpr12 bpr11 bpr10 internal bus f
173 chapter 8 serial interface function (1) dedicated baud rate generator (brg0 and brg1) the dedicated baud rate generator brg consists of an 8-bit timer (tmbrg0, tmbrg1) that generates a shift clock for transmission/reception, a compare register (brg0, brg1), and a prescaler. (a) input clock system clock f is input to the brg0 and brg1 register. (b) set-up value of brg0 and brg1 register (i) uart if the dedicated baud rate generator is specified for uart, the actual baud rate can be calculated by the following expression, because a sampling rate of x16 is used: baud rate = [bps] where, f : system clock frequency [hz] m : timer-counted value (1 m 256 note ) : set by brg0, brg1 n : prescaler set-up value (n = 0, 1, 2, 3, 4) : set by bprm0, bprm1 note m = 256 is set by writing 0 to the brg register. (ii) csi0 to csi2 if the dedicated baud rate generator is specified for csi0 to csi2, the actual baud rate can be calculated by the following expression: baud rate = [bps] where, f : system clock frequency [hz] m : timer-counted value (1 m 256 note ) : set by brg0, brg1 n : prescaler set-up value (n = 0, 1, 2, 3, 4) : set by bprm0, bprm1 note m = 256 is set by writing 0 to the brg register. table 8-2 shows the set-up values of the baud rate generator when the typical clocks are used: f 2 x m x 2 n x 16 x 2 f 2 x m x 2 n x 2
174 chapter 8 serial interface function table 8-2. brg set-up values note cannot be used because the error is too great. uart 110 150 300 600 1200 2400 4800 9600 10400 19200 38400 76800 153600 brg0 222 163 163 163 163 163 81 41 38 20 10 5 2 bpr 4 4 3 2 1 0 0 0 0 0 0 0 0 error 0.02 % 0.15 % 0.15 % 0.15 % 0.15 % 0.15 % 0.47 % 0.76 % 1.16 % 1.73 % 1.73 % 1.73 % 27.2 % error 0.03 % 0.16 % 0.16 % 0.16 % 0.16 % 0.16 % 0.16 % 0.16 % 1.16 % 1.16 % 6.99 % note C C brg0 142 208 208 208 208 104 52 26 24 13 7 C C bpr 4 3 2 1 0 0 0 0 0 0 0 C C error 0.12 % 0.12 % 0.12 % 0.12 % 0.12 % 0.12 % 0.12 % 0.12 % 0.12 % 0.12 % 8.4 % note C C baud rate [bps] csi 1760 2400 4800 9600 19200 38400 76800 153600 166400 307200 614400 1228800 2457600 bpr 3 3 2 1 0 0 0 0 0 0 0 C C brg0 240 176 176 176 176 88 44 22 20 11 6 C C uart 110 150 300 600 1200 2400 4800 9600 10400 19200 38400 76800 153600 bpr 4 4 3 2 1 0 0 0 0 0 0 0 0 error 0.07 % 0.0 % 0.0 % 0.0 % 0.0 % 0.0 % 0.0 % 0.0 % 0.7 % 0.0 % 0.0 % 0.0 % 25.0 % note error 0.26 % 0.0 % 0.0 % 0.0 % 0.0 % 0.0 % 0.0 % 0.0 % 1.5 % 0.0 % 0.0 % 0.0 % 0.0 % f = 20 mhz baud rate [bps] f = 14.746 mhz error 0.25 % 0.16 % 0.16 % 0.16 % 0.16 % 0.16 % 0.16 % 1.36 % 0.16 % 1.73 % 1.73 % 1.73 % 1.73 % brg0 178 130 130 130 130 130 65 33 30 16 8 4 2 brg0 131 192 192 192 192 96 48 24 22 12 6 3 2 bpr 4 3 2 1 0 0 0 0 0 0 0 0 0 bpr 3 3 2 1 0 0 0 0 0 0 0 0 0 brg0 175 128 128 128 128 64 32 16 15 8 4 2 1 csi 1760 2400 4800 9600 19200 38400 76800 153600 166400 307200 614400 1228800 2457600 f = 25 mhz f = 16 mhz f = 13.5mhz f = 9.830 mhz error 0.02 % 0.15 % 0.15 % 0.15 % 0.15 % 0.47 % 0.76 % 1.73 % 1.16 % 1.73 % 1.73 % 15.2 % note C bpr 3 3 2 1 0 0 0 0 0 0 0 0 C brg0 222 163 163 163 163 81 41 20 19 10 5 3 C f = 12.5mhz bpr 3 3 2 1 0 0 0 0 0 0 0 0 C error 0.08 % 0.0 % 0.0 % 0.0 % 0.0 % 0.0 % 0.0 % 0.0 % 2.6 % 0.0 % 0.0 % 16.7 % note C brg0 218 160 160 160 160 80 40 20 18 10 5 3 C f = 12.288 mhz
175 chapter 8 serial interface function (c) error of baud rate generator the error of the baud rate generator is calculated as follows: error [%] = C1 x 100 example: (9520/9600C1) x 100 = C0.833 [%] (5000/4800C1) x 100 = +4.167 [%] (2) allowable error range of baud rate generator the allowable error range depends on the number of bits of one frame. the basic limit is 5 % of baud rate error and 4.5 % of sample timing with an accuracy of 16 bits. however, the practical limit should be 2.3 % of baud rate error, assuming that both the transmission and reception sides contain an error. actual baud rate (baud rate with error) desired baud rate (normal baud rate)
176 chapter 8 serial interface function 8.4.2 baud rate generator register 0, 1 (brg0, brg1) this is an 8-bit compare register that sets a timer/count value for the dedicated baud rate generator. this register can be read/written in 8- or 1-bit units. caution the internal timer (tmbrgn) (n = 0 and 1) is cleared by writing the brgn (n = 0 and 1) register. therefore, do not rewrite or program the brgn register during transmission/reception operation. 8.4.3 baud rate generator prescaler mode register 0, 1 (bprm0, bprm1) this register controls the timer/count operation of the dedicated baud rate generator and selects a count clock. it can be read/written in 8- or 1-bit units. bit position bit name function 7 brcem baud rate generator count enable controls count operation of brg. 0: stops count operation with cleared 1: enables count operation 2 to 0 bprm2 to baud rate generator prescaler bprm0 specifies count clock input to tmbrg. bpr02 bpr01 bpr00 count clock 00 0 f /2 (n = 0) 00 1 f /4 (n = 1) 01 0 f /8 (n = 2) 01 1 f /16 (n = 3) 1x x f /32 (n = 4) n: set value of prescaler, f : system clock caution do not change the count clock during transmission/reception operation. remark m = 0, 1 address fffff084h 7 brg07 brg0 6 brg06 5 brg05 4 brg04 3 brg03 2 brg02 1 brg01 0 brg00 at reset undefined address fffff094h 7 brg17 brg1 6 brg16 5 brg15 4 brg14 3 brg13 2 brg12 1 brg11 0 brg10 at reset undefined address fffff086h 7 brce0 bprm0 6 0 5 0 4 0 3 0 2 bpr02 1 bpr01 0 bpr00 at reset 00h address fffff096h 7 brce1 bprm1 6 0 5 0 4 0 3 0 2 bpr12 1 bpr11 0 bpr10 at reset 00h
177 chapter 9 port function chapter 9 port function 9.1 features the ports of the v852 have the following features: number of pins: input : 1 i/o : 67 multiplexed with i/o pins of other peripheral functions can be set in input/output mode in 1-bit units noise elimination edge detection
178 chapter 9 port function 9.2 basic configuration of port the v852 is provided with a total of 67 input/output port pins that make up ports 0 to 10. the configuration of the v852s ports is shown below. p00 p07 port 0 p10 p17 port 1 p21 p27 port 2 p20 p30 p37 port 3 p40 p47 port 4 p50 p57 port 5 p60 p67 port 6 p90 p97 p100 p103 port 9 port 10 to to to to to to to to to
179 chapter 9 port function note the port 2 is a 7-bit i/o port. caution when switching a port that operates as an output pin or input/output pin during control mode, from port mode to control mode, the procedure below must be followed. <1> set the inactive level of the the signal which is output as control mode to the relevant bit of port n (pn) (n = 0, 2, 3 to 6, 9, 10). <2> change to control mode by port n mode control register (pmcn). if <1> is not done, a momentary output of the contents of port n (pn) may occur on changing from port mode to control mode. (1) function of each port the ports of the v852 have the functions shown in the table below. in addition to port functions, some ports have functions as internal hardware input/output pins, when placed in the control mode. port name port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 9 port 10 remarks can be set in port or control mode in 1-bit units function in control mode real-time pulse unit (rpu) input/output external interrupt request input C external interrupt request input serial interface (csi2) input/output serial interface (uart, csi0, csi1) input/output address/data bus (ad0 to ad7) for external memory address/data bus (ad8 to ad15) for external memory address bus (a16 to a23) for external memory control signal output for external memory control signal input/output for system expansion port function 8-bit note i/o port (can specify i/o bitwise) fixed to port mode can be set in port or control mode in 1-bit units can be set in port or control mode in 8-bit units can be set in port or control mode in 2-bit units can be set in port or control mode in 5-, 2-, or 1-bit units can be set in port or control mode in 1-bit units 4-bit i/o port (can specify i/o bitwise)
180 chapter 9 port function (2) function of ports after reset and register to set port/control mode (1/2) port pin function at reset (parentheses indicate i/o) register single-chip mode rom-less mode to set mode port 0 p00/to10 p00 (input) pmc0 p01/to11 p01 (input) p02/tclr1 p02 (input) p03/ti1 p03 (input) p04/intp10 p04 (input) p05/intp11 p05 (input) p06/intp12 p06 (input) p07/intp13 p07 (input) port 1 p10-p17 p10-p17 (all inputs) port 2 p20/nmi nmi (input) p21/intp00 p21 (input) pmc2 p22/intp01 p22 (input) p23/intp02 p23 (input) p24/intp03 p24 (input) p25/so2 p25 (input) p26/si2 p26 (input) p27/sck2 p27 (input) port 3 p30/so0 p30 (input) pmc3 p31/si0 p31 (input) p32/sck0 p32 (input) p33/txd p33 (input) p34/rxd p34 (input) p35/so1 p35 (input) p36/si1 p36 (input) p37/sck1 p37 (input) port 4 p40/ad0-p47/ad7 p40-p47 (all inputs) ad0-ad7 mm port 5 p50/ad8-p57/ad15 p50-p57 (all inputs) ad8-ad15 mm port 6 p60/a16-p67/a23 p60-p67 (all inputs) a16-a23 mm port 9 p90/lben p90 (input) lben mm p91/uben p91 (input) uben p92/r/w p92 (input) r/w p93/dstb p93 (input) dstb p94/astb p94 (input) astb p95/st0 p95 (input) p96/st1 p96 (input) p97 p97 (input)
181 chapter 9 port function (2/2) port pin function at reset (parentheses indicate i/o) register single-chip mode rom-less mode to set mode port 10 p100/hldak p100 (input) pmc10 p101/hldrq p101 (input) p102 p102 (input) p103 p103 (input)
182 chapter 9 port function 9.3 port pin function 9.3.1 port 0 port 0 is an 8-bit input/output port that can be set in the input or output mode in 1-bit units. bit position bit name function 7 to 0 p0n port 0 (n = 7 to 0) i/o port in addition to the function as a general i/o port, this port can also be used to input/output signals of the real-time pulse unit (rpu) and input external interrupt requests, when placed in the control mode. operation in control mode port control mode remarks port 0 p00 to10 real-time pulse unit (rpu) output p01 to11 p02 tclr1 real-time pulse unit (rpu) input p03 ti1 p04 to p07 intp10 to intp13 external interrupt input 7 p07 p0 6 p06 5 p05 4 p04 3 p03 2 p02 1 p01 0 p00 address fffff000h at reset undefined
183 chapter 9 port function (1) hardware configuration figure 9-1. block diagram of p00, p01 (port 0) remark n = 0, 1 figure 9-2. block diagram of p02 to p07 (port 0) remark n = 2 to 7 wr pmc wr pm pmc0n pm0n p0n wr port rd in address to1n p0n selector selector selector internal bus wr pmc wr pm pmc0n pm0n p0n wr port rd in p0n selector selector internal bus intp10 to intp13, tclr1, ti1 noise elimination edge detection address
184 chapter 9 port function (2) setting input/output mode and control mode the input/output mode of port 0 is set by port mode register 0 (pm0). the control mode is set by port mode control register 0 (pmc0). port 0 mode register (pm0) this register can be read/written in 8- or 1-bit units. bit position bit name function 7 to 0 pm00 to pm07 port mode sets p00 to p07 pins in input/output mode. 0: output mode (output buffer on) 1: input mode (output buffer off) 7 pm07 pm0 6 pm06 5 pm05 4 pm04 3 pm03 2 pm02 1 pm01 0 pm00 address fffff020h at reset ffh
185 chapter 9 port function port 0 mode control register (pmc0) this register can be read/written in 8- or 1-bit units. bit position bit name function 7 to 4 pmc07 to pmc04 port mode control indicates operation mode of p0n pin. 0: i/o port mode 1: external interrupt request input (intp13 to intp10) 3 pmc03 port mode control indicates operation mode of p03 pin. 0: i/o port mode 1: ti1 input mode 2 pmc02 port mode control indicates operation mode of p02 pin. 0: i/o port mode 1: tclr1 input mode 1 pmc01 port mode control indicates operation mode of p01 pin. 0: i/o port mode 1: to11 output mode 0 pmc00 port mode control indicates operation mode of p00 pin. 0: i/o port mode 1: to10 output mode 7 pmc07 pmc0 6 pmc06 5 pmc05 4 pmc04 3 pmc03 2 pmc02 1 pmc01 0 pmc00 address fffff040h at reset 00h
186 chapter 9 port function 9.3.2 port 1 port 1 is an 8-bit input/output port that can be set in the input or output mode in 1-bit units. bit position bit name function 7 to 0 p1n port 1 (n = 7 to 0) i/o port port 1 is not multiplexed with other functions and is fixed in the port mode. port control mode remarks port 1 p10 to p17 C fixed in port mode (1) hardware configuration figure 9-3. block diagram of p10 to p17 (port 1) remark n = 0 to 7 7 p17 p1 6 p16 5 p15 4 p14 3 p13 2 p12 1 p11 0 p10 address fffff002h at reset undefined wr pm address pm1n p1n selector selector internal bus wr port rd in p1n
187 chapter 9 port function (2) setting input/output mode the input/output mode of port 1 is set by port mode register 1 (pm1). port 1 mode register (pm1) this register can be read/written in 8- or 1-bit units. bit position bit name function 7 to 0 pm1n port mode (n = 7 to 0) sets p1n pin in input/output mode. 0: output mode (output buffer on) 1: input mode (output buffer off) 9.3.3 port 2 port 2 is an 8-bit input/output port that can be set in the input or output mode in 1-bit units. however, p20 always operates as a nmi when an edge is input. bit position bit name function 7 to 1 p2n port 2 (n = 7 to 1) i/o port 0 p20 fixed to nmi input mode in addition to the function as a port, this port can also be used to input external interrupt requests and clocked serial interface (csi) i/o in the control mode. operation in control mode port control mode remarks port 2 p20 nmi non-maskable interrupt request input p21 to 24 intp00 to intp03 external interrupt request input p25 so2 i/o for clocked serial interface (csi2) p26 si2 p27 sck2 7 pm17 pm1 6 pm16 5 pm15 4 pm14 3 pm13 2 pm12 1 pm11 0 pm10 address fffff022h at reset ffh 7 p27 p2 6 p26 5 p25 4 p24 3 p23 2 p22 1 p21 0 p20 address fffff004h at reset undefined
188 chapter 9 port function (1) hardware configuration figure 9-4. block diagram of p20 (port 2) figure 9-5. block diagram of p21 to p24 (port 2) remark n = 1 to 4 rd in p20 selector internal bus noise elimination address 1 edge detection nmi wr pmc wr pm pmc2n pm2n p2n wr port selector intp00 to intp03 internal bus noise elimination edge detection rd in selector address p2n
189 chapter 9 port function figure 9-6. block diagram of p25 (port 2) figure 9-7. block diagram of p26 (port 2) wr pmc wr pm pmc25 pm25 p25 wr port rd in address so2 p25 selector selector selector internal bus wr pmc wr pm pmc26 pm26 p26 wr port rd in address p26 selector selector internal bus si2
190 chapter 9 port function figure 9-8. block diagram of p27 (port 2) wr pmc wr pm pmc27 pm27 p27 wr port rd in p27 selector selector internal bus sck2 input address selector sck2 output
191 chapter 9 port function (2) setting input/output mode and control mode the input/output mode of port 2 is set by port mode register 2 (pm2). the control mode is set by port mode control register 2 (pmc2). p20 is fixed in the nmi input mode. port 2 mode register (pm2) this register can be read/written in 8- or 1-bit units. however, bit 0 is fixed to 1 by hardware. even if 0 is written to this bit, it is ignored. bit position bit name function 7 to 1 pm2n port mode (n = 7 to 1) sets p2n pin in input/output mode. 0: output mode (output buffer on) 1: input mode (output buffer off) 7 pm27 pm2 6 pm26 5 pm25 4 pm24 3 pm23 2 pm22 1 pm21 0 1 address fffff024h at reset ffh
192 chapter 9 port function port 2 mode control register (pmc2) this register can be read/written in 8- or 1-bit units. however, bit 0 is fixed to 1 by hardware. if 0 is written to this bit, it is ignored. bit position bit name function 7 pmc27 port mode control sets operation mode of p27 pin. 0: i/o port mode 1: sck2 i/o mode 6 pmc26 port mode control sets operation mode of p26 pin. 0: i/o port mode 1: si2 input mode 5 pmc25 port mode control sets operation mode of p25 pin. 0: i/o port mode 1: so2 output mode 4 pmc24 port mode control sets operation mode of p24 pin. 0: i/o port mode 1: intp03 input mode 3 pmc23 port mode control sets operation mode of p23 pin. 0: i/o port mode 1: intp02 input mode 2 pmc22 port mode control sets operation mode of p22 pin. 0: i/o port mode 1: intp01 input mode 1 pmc21 port mode control sets operation mode of p21 pin. 0: i/o port mode 1: intp00 input mode 9.3.4 port 3 port 3 is an 8-bit input/output port that can be set in the input or output mode in 1-bit units. bit position bit name function 7 to 0 p3n port 3 (n = 7 to 0) i/o port in addition to the function as a port, this port can also be used as the input/output lines of the serial interface (uart, csi), when placed in the control mode. 7 pmc27 pmc2 6 pmc26 5 pmc25 4 pmc24 3 pmc23 2 pmc22 1 pmc21 0 1 address fffff044h at reset 01h 7 p37 p3 6 p36 5 p35 4 p34 3 p33 2 p32 1 p31 0 p30 address fffff006h at reset undefined
193 chapter 9 port function operation in control mode port control mode remarks port 3 p30 so0 i/o for serial interface (uart, csi0, csi1) p31 si0 p32 sck0 p33 txd p34 rxd p35 so1 p36 si1 p37 sck1 (1) hardware configuration figure 9-9. block diagram of p30, p33, p35 (port 3) remark n = 0, 3, 5 wr pmc wr pm pmc3n pm3n p3n wr port rd in address so0, so1, txd p3n selector selector selector internal bus
194 chapter 9 port function figure 9-10. block diagram of p31, p36 (port 3) remark n = 1, 6 m = 0, 1 figure 9-11. block diagram of p32, p37 (port 3) remark n = 2, 7 m = 0, 1 wr pmc wr pm pmc3n pm3n p3n wr port rd in address p3n selector selector internal bus sim wr pmc wr pm pmc3n pm3n p3n wr port rd in p3n selector selector internal bus sckm input address selector sckm output
195 chapter 9 port function figure 9-12. block diagram of p34 (port 3) (2) setting input/output mode and control mode the input/output mode of port 3 is set by port mode register 3 (pm3). the control mode is set by port mode control register 3 (pmc3). port 3 mode register (pm3) this register can be read/written in 8- or 1-bit units. bit position bit name function 7 to 0 pm3n port mode (n = 7 to 0) sets p3n pin in input/output mode. 0: output mode (output buffer on) 1: input mode (output buffer off) wr pmc wr pm pmc34 pm34 p34 wr port rd in address p34 selector selector internal bus rxd 7 pm37 pm3 6 pm36 5 pm35 4 pm34 3 pm33 2 pm32 1 pm31 0 pm30 address fffff026h at reset ffh
196 chapter 9 port function 7 pmc37 pmc3 6 pmc36 5 pmc35 4 pmc34 3 pmc33 2 pmc32 1 pmc31 0 pmc30 address fffff046h at reset 00h port 3 mode control register (pmc3) this register can be read/written in 8- or 1-bit units. bit position bit name function 7 pmc37 port mode control sets operation mode of p37 pin. 0: i/o port mode 1: sck1 i/o mode 6 pmc36 port mode control sets operation mode of p36 pin. 0: i/o port mode 1: si1 input mode 5 pmc35 port mode control sets operation mode of p35 pin. 0: i/o port mode 1: so1 output mode 4 pmc34 port mode control sets operation mode of p34 pin. 0: i/o port mode 1: rxd input mode 3 pmc33 port mode control sets operation mode of p33 pin. 0: i/o port mode 1: txd output mode 2 pmc32 port mode control sets operation mode of p32 pin. 0: i/o port mode 1: sck0 input/output mode 1 pmc31 port mode control sets operation mode of p31 pin. 0: i/o port mode 1: si0 input mode 0 pmc30 port mode control sets operation mode of p30 pin. 0: i/o port mode 1: so0 output mode
197 chapter 9 port function 9.3.5 port 4 port 4 is an 8-bit input/output port that can be set in the input or output mode in 1-bit units. bit position bit name function 7 to 0 p4n port 4 (n = 7 to 0) i/o port in addition to the function as a general i/o port, this port also serves as an external address/data bus, when placed in the control mode. operation in control mode port control mode remarks port 4 p40 to 47 ad0 to ad7 address/data bus for external memory (1) hardware configuration figure 9-13. block diagram of p40 to p47 (port 4) remark n = 0 to 7 7 p47 p4 6 p46 5 p45 4 p44 3 p43 2 p42 1 p41 0 p40 address fffff008h at reset undefined wr pm pm4n p4n wr port ad0 to ad7 p4n input/ output control circuit internal bus rd in mode0, mode1 mm0 to mm2
198 chapter 9 port function (2) setting input/output mode and control mode the input/output mode of port 4 is set by port mode register 4 (pm4). the control mode (external expansion mode) is set by mode specification pins mode0 and mode1, and memory expansion mode register (mm: refer to 3.4.6 (1) ). port 4 mode register (pm4) this register can be read/written in 8- or 1-bit units. bit position bit name function 7 to 0 pm4n port mode (n = 7 to 0) sets p4n pin in input/output mode. 0: output mode (output buffer on) 1: input mode (output buffer off) operation mode of port 4 bit of mm register operation mode mm2 mm1 mm0 p40 p41 p42 p43 p44 p45 p46 p47 0 0 0 port 011 1 0 0 address/data bus 1 0 1 (ad0 to ad7) 110 111 others rfu (reserved) for the details of mode selection by the mode0 and mode1 pins, refer to 3.3.2 specifying operation mode . when mode0 and mode1 = 00 (rom-less mode), mm0 to mm2 bits are initialized to 111 at system reset, enabling the external expansion mode. external expansion can be disabled by programming the mm0 to mm2 bits and setting the port mode. if mm0 to mm2 are cleared to 000, the subsequent external instruction cannot be fetched. 7 pm47 pm4 6 pm46 5 pm45 4 pm44 3 pm43 2 pm42 1 pm41 0 pm40 address fffff028h at reset ffh
199 chapter 9 port function 9.3.6 port 5 port 5 is an 8-bit input/output port that can be set in the input or output mode in 1-bit units. bit position bit name function 7 to 0 p5n port 5 (n = 7 to 0) i/o port in addition to the function as a general i/o port, this port also serves as an external address/data bus, when placed in the control mode. operation in control mode port control mode remarks port 5 p50 to 57 ad8 to ad15 address/data bus for external memory (1) hardware configuration figure 9-14. block diagram of p50 to p57 (port 5) remark n = 0 to 7 7 pm57 p5 6 p56 5 p55 4 p54 3 p53 2 p52 1 p51 0 p50 address fffff00ah at reset undefined wr pm pm5n p5n wr port ad8 to ad15 p5n input/ output control circuit internal bus rd in mode0, mode1 mm0 to mm2
200 chapter 9 port function (2) setting input/output mode and control mode the input/output mode of port 5 is set by port mode register 5 (pm5). the control mode (external expansion mode) is set by mode specification pins mode0 and mode1, and memory expansion mode register (mm: refer to 3.4.6 (1) ). port 5 mode register (pm5) this register can be read/written in 8- or 1-bit units. bit position bit name function 7 to 0 pm5n port mode (n = 7 to 0) sets p5n pin in input/output mode. 0: output mode (output buffer on) 1: input mode (output buffer off) operation mode of port 5 bit of mm register operation mode mm2 mm1 mm0 p50 p51 p52 p53 p54 p55 p56 p57 0 0 0 port 011 1 0 0 address/data bus 1 0 1 (ad8 to ad15) 110 111 others rfu (reserved) 7 pm57 pm5 6 pm56 5 pm55 4 pm54 3 pm53 2 pm52 1 pm51 0 pm50 address fffff02ah at reset ffh
201 chapter 9 port function 9.3.7 port 6 port 6 is an 8-bit input/output port that can be set in the input or output mode in 1-bit units. bit position bit name function 7 to 0 p6n port 6 (n = 7 to 0) i/o port in addition to the function as a general i/o port, this port also serves as an external address bus, when placed in the control mode. operation in control mode port control mode remarks port 6 p60 to 67 a16 to a23 address bus for external memory (1) hardware configuration figure 9-15. block diagram of p60 to 67 (port 6) remark n = 0 to 7 7 p67 p6 6 p66 5 p65 4 p64 3 p63 2 p62 1 p61 0 p60 address fffff00ch at reset undefined wr pm pm6n p6n wr port a16 to a23 p6n input/ output control circuit internal bus rd in mode0, mode1 mm0 to mm2
202 chapter 9 port function (2) setting input/output mode and control mode the input/output mode of port 6 is set by port mode register 6 (pm6). the control mode (external expansion mode) is set by mode specification pins mode0 and mode1, and memory expansion mode register (mm: refer to 3.4.6 (1) ). port 6 mode register (pm6) this register can be read/written in 8- or 1-bit units. bit position bit name function 7 to 0 pm6n port mode (n = 7 to 0) sets p6n pin in input/output mode. 0: output mode (output buffer on) 1: input mode (output buffer off) operation mode of port 6 bit of mm register operation mode mm2 mm1 mm0 p60 p61 p62 p63 p64 p65 p66 p67 0 0 0 port 011 100 101 110 111 others rfu (reserved) 9.3.8 port 9 port 9 is an 8-bit input/output port that can be set in the input or output mode in 1-bit units. bit position bit name function 7 to 0 p9n port 9 (n = 7 to 0) i/o port a16 a17 a18 a19 a20 a21 a23 a22 7 pm67 pm6 6 pm66 5 pm65 4 pm64 3 pm63 2 pm62 1 pm61 0 pm60 address fffff02ch at reset ffh 7 p97 p9 6 p96 5 p95 4 p94 3 p93 2 p92 1 p91 0 p90 address fffff012h at reset undefined
203 chapter 9 port function in addition to the function as a general i/o port, this port can also be used to output external bus control signals, when placed in the control mode. operation in control mode port control mode remarks port 9 p90 lben control signal output for external memory p91 uben p92 r/w p93 dstb p94 astb p95 st0 p96 st1 p97 C fixed in port mode (1) hardware configuration figure 9-16. block diagram of p90 to p97 (port 9) remark n = 0 to 7 wr pm pm9n p9n wr port p9n input/ output control circuit internal bus rd in mode0, mode1 mm0 to mm3 lben, uben, r/w, dstb, astb, st0, st1
204 chapter 9 port function 7 pm97 pm9 6 pm96 5 pm95 4 pm94 3 pm93 2 pm92 1 pm91 0 pm90 address fffff032h at reset ffh (2) setting input/output mode and control mode the input/output mode of port 9 is set by port mode register 9 (pm9). the control mode (external expansion mode) is set by mode specification pins mode0 and mode1, and memory expansion mode register (mm: refer to 3.4.6 (1) ). port 9 mode register (pm9) this register can be read/written in 8- or 1-bit units. bit position bit name function 7 to 0 pm9n port mode (n = 7 to 0) sets p9n pin in input/output mode. 0: output mode (output buffer on) 1: input mode (output buffer off) operation mode of port 9 p90 to p94 p95, p96 bit of mm register operation mode mm3 operation mode p95 p96 mm2 mm1 mm0 p90 p91 p92 p93 p94 0 port mode port 0 0 0 port 1 external expansion mode st0 st1 0 1 1 lben uben r/w dstb astb 100 101 110 111 others rfu (reserved)
205 chapter 9 port function 9.3.9 port 10 port 10 is a 4-bit input/output port that can be set in the input or output mode in 1-bit units. bit position bit name function 3 to 0 p10n port 10 (n = 3 to 0) i/o port when port 10 is accessed in 8-bit units for write, the higher 4 bits are ignored. when it is accessed in 8-bit units for read, undefined data is read. in addition to the function as a port, this port can also be used to input and output external control signals to a bus master or asic device, when placed in the control mode. operation in control mode port control mode remarks port 10 p100 hldak bus hold control signal input/output p101 hldrq p102, p103 C fixed in port mode (1) hardware configuration figure 9-17. block diagram of p100, p103 (port 10) note rfu is an undefined value. remark n = 0, 3 7 p10 6 5 4 3 p103 2 p102 1 p101 0 p100 address fffff014h at reset undefined wr pmc wr pm pmc10n pm10n p10n wr port rd in address hldak, rfu note p10n selector selector selector internal bus
206 chapter 9 port function figure 9-18. block diagram of p101 (port 10) figure 9-19. block diagram of p102 (port 10) wr pmc wr pm pmc101 pm101 p101 wr port rd in address p101 selector selector internal bus hldrq wr pm pm102 p102 wr port rd in p102 selector selector internal bus address
207 chapter 9 port function (2) setting input/output mode and control mode the input/output mode of port 10 is set by port mode register 10 (pm10). the control mode is set by port mode control register 10 (pmc10). port 10 mode register (pm10) this register can be read/written in 8- or 1-bit units. bit position bit name function 3 to 0 pm10n port mode (n = 3 to 0) sets p10n pin in input/output mode. 0: output mode (output buffer on) 1: input mode (output buffer off) port 10 mode control register (pmc10) this register can be read/written in 8- or 1-bit units. bit position bit name function 1 pmc101 port mode control sets operation mode of p101 pin. 0: i/o port mode 1: hldrq input mode 0 pmc100 port mode control sets operation mode of p100 pin. 0: i/o port mode 1: hldak output mode 7 1 pm10 6 1 5 1 4 1 3 pm103 2 pm102 1 pm101 0 pm100 address fffff034h at reset ffh 7 0 pmc10 6 0 5 0 4 0 3 0 2 0 1 pmc101 0 pmc100 address fffff054h at reset 00h
208 chapter 9 port function 9.4 noise elimination circuit pins operating with valid edge inputs in the control mode are provided with timing control circuits for maintaining the following noise elimination time. a signal input changed less than the noise elimination time is not accepted internally. pin noise elimination time p20/nmi note analog delay (60 ns to 220 ns) p02/tclr1 2 to 3 system clocks p03/ti1 p04/intp10 p05/intp11 p06/intp12 p07/intp13 p21/intp00 p22/intp01 p23/intp02 p24/intp03 note the p20/nmi pin is used to release the stop mode. in the stop mode, the clock control timing circuit is not used because the clock is stopped. figure 9-20. example of noise elimination timing clkout input signal internal signal rising edge detected falling edge detected 3 clocks max. 2 clocks min.
209 chapter 10 reset function chapter 10 reset function when the low-level is input to the reset pin, the system is reset and each on-chip hardware is initialized to the initial state. when the reset pin changes from low-level to high-level, the reset state is released and the cpu starts executing the program. initialize the contents of each register in the program as necessary. 10.1 features analog noise elimination circuit (delay of approx. 60 to 220 ns) provided on reset pin 10.2 pin function during the reset state, all the pins (except clkout, reset, x2, v dd , v ss , cv dd , and cv ss pins) are in the high- impedance state. when an external memory is connected, a pull-up (or pull-down) resistor must be connected to each pin of ports 4, 5, 6, and 9. otherwise, the memory contents may be lost if these pins go into a high-impedance state. also treat signal outputs of the on-chip peripheral i/o function and the output port so that they will not be affected. the internal system clock continues to generate the clock signal at clkout pin while the device is in the reset state. table 10-1 shows the operating status of each pin during the reset period. table 10-1. operating status of each pin during reset period pin operating status ad0 to ad15 hi-z a16 to a23 lben, uben r/w dstb astb st0, st1 hldrq C hldak hi-z wait C clkout clock output
210 chapter 10 reset function (1) accepting reset signal note the internal system reset signal remains active for the duration of at least 4 system clocks after the reset condition is removed from the reset pin. (2) power-on reset in the reset operations at power-on (power is turned on), there is a need to maintain oscillation stabilization time of more than 10 ms from the start up of the power until reset is acknowledged to the low-level width of the reset pin. 10.3 initialize table 10-2 shows the initial value of each register after reset. the contents of the registers must be initialized in the program as necessary. especially, set the following registers as necessary because they are related to system setting: power save control register (psc) ... x1 and x2 pin function, clkout pin operation, etc. data wait control register (dwc) ... number of data wait states caution in table 10-2, undefined means an undefined value due to power-on reset or data corruption when a falling edge of reset coincides with a data write operation. the previous status of data is retained by a falling edge of reset due to the cases other than the above. reset pin internal system reset signal analog delay eliminated as noise analog delay analog delay note reset accepted reset released v dd reset pin oscillation stabilization time analog delay reset released
211 chapter 10 reset function table 10-2. initial values of each register at reset register initial value at reset r0 00000000h r1 to r31 undefined pc 00000000h psw 00000020h eipc undefined eipsw undefined fepc undefined fepsw undefined ecr 00000000h internal ram undefined port input/output latch (p0 to p6, p9, p10) undefined mode register (pm0 to 6, pm9, pm10) ffh mode control register (pmc0, pmc3, pmc10) 00h (pmc2) 01h memory expansion mode register (mm) b0h or b7h clock generator system status register (sys) 0000000xb power save control register (psc) 00h real-time pulse unit timer unit mode register (tum1) 0000h timer control register (tmc1, tmc4) 00h timer output control register 1 (toc1) 00h timer (tm1, tm4) 0000h capture/compare register (cc10 to cc13) undefined compare register 4 (cm4) undefined timer overflow status register (tovs) 00h serial interface asynchronous serial interface mode register 00 (asim00) 80h asynchronous serial interface mode register 01 (asim01) 00h asynchronous serial interface status register 0 (asis0) 00h receive buffer (rxb0, rxb0l) undefined transmit shift register (txs0, txs0l) undefined clocked serial interface mode register n (csimn) (n = 0 to 2) 00h serial i/o shift register n (sion) (n = 0 to 2) undefined baud rate generator register 0, 1 (brg0, brg1) undefined baud rate generator prescaler mode register 0, 1 (bprm0, bprm1) 00h interrupt/exception processing function interrupt control register (xxcn) 47h in-service priority register (ispr) 00h external interrupt mode register (intm0, intm1, intm2) 00h memory management function data wait control register (dwc) ffffh bus cycle control register (bcc) aaaah power save control command register (prcmd) undefined power save control register (psc) 00h remark x: undefined
212 chapter 10 reset function caution in the above table, undefined means the undefined value after power-on reset, or the undefined value caused by data destruction due to synchronization of reset input and data write timings. with other reset inputs, the data immediately before reset input is maintained.
213 chapter 11 prom mode read mode operation mode pin programming mode chapter 11 prom mode the prom model of the v852 is provided with 90 kb of one-time prom. instruction fetch to internal rom is accessed in 1 clock in the same manner as the mask rom model. 11.1 prom mode the prom mode is entered by the setting mode0 and mode1 pins. connect the pins not used in this mode as described in section 1.5.2 prom programming mode . v pp mode1 mode0 operation mode 5.0 v 1 1 prom mode (read mode) 12.5 v 1 1 prom mode (programming mode) v pp : programming voltage 11.2 operation mode operation in the prom programming mode is determined by the setting of the pins shown in the following table. p25/ce p26/oe p27/pgm v pp v dd p47/d7 to p40/d0 read l l h +5.0 v +5.0 v data output output disable l h x hi-z note standby h x x page data latch h l h +12.5 v +6.5 v data input page program h h l hi-z byte program l h l data input program verify l l h data output program inhibit x l l hi-z note hh v pp : programming voltage (12.5 v) x : optional note in this case, the address input is invalid, and 1/0 can be input. (1) read mode the read mode is set when ce = l and oe = l.
214 chapter 11 prom mode (2) output disable mode the data output goes into a high-impedance state when ce = l and oe = h, and the output disable mode is set. if two or more m pd70p3002s are connected to the data bus, any one of the devices can be read by controlling the oe pin. (3) standby mode the standby mode is set when ce = h. in this mode, the data output goes into a high-impedance state regardless of the status of oe. (4) page data latch mode the page data latch mode is set when ce = h, oe = l, and pgm = h at the beginning of the page write mode. in this mode, data of 1 page and 4 bytes is latched to the internal address/data latch circuit. (5) page write mode page write is executed in the page write mode by applying a 0.1-ms program pulse (active low) to the pgm pin with ce = h and oe = h, after an address and data of 1 page and 4 bytes have been latched. after that, the program can be verified when ce = l and oe = l. if the program cannot be written by one program pulse, write and verify are repeatedly executed x times (x 10). (6) byte write mode byte write is executed by applying a 0.1-ms program pulse (active low) to the pgm pin with ce = l and oe = h. after that, the program can be verified when oe = l. if the program cannot be written by one program pulse, write and verify are repeatedly executed x times (x 10). (7) program verify mode the program verify mode is set by setting ce = l, pgm = h, and oe = l. use this mode to the check if the program has been correctly written. (8) program inhibit mode the program inhibit mode is used to write data to one of the m pd70p3002s whose oe, v pp , and d0 to d7 pins are connected in parallel. to write data, the page write mode or byte write mode is used. at this time, data cannot be written to a device whose pgm pin is high.
215 chapter 11 prom mode 11.3 prom write procedure page programming mode flowchart start x = 0 supplies program pulse latch x = x + 1 supplies write data latch address = address + 1 latch address = address + 1 latch address = address + 1 v dd = 5 v v pp = 5 v mode1 = mode0 = h supplies initial address v dd = 6.5 v v pp = 12.5 v end of write v dd = 4.5 to 5.5 v v pp = v dd 4-byte verify address = iast address verifies all bytes defective x = 10? address = address + 1 fail fail yes pass all pass pass no yes no
216 chapter 11 prom mode page programming mode timing page data latch page program program verify data input data output a2 to a16 a0, a1 d0 to d7 v dd v pp + 6.5 v + 12.5 v v dd v dd v ih v il ce v ih v il pgm v ih v il oe
217 chapter 11 prom mode byte programming mode flowchart start x = 0 x = x + 1 supplies write data supplies program pulse v dd = 5 v v pp = 5 v mode1 = mode0 = h supplies initial address v dd = 6.5 v v pp = 12.5 v end of write v dd = 4.5 to 5.5 v v pp = v dd verify address = iast address verifies all bytes defective x = 10? address = address + 1 fail fail yes pass all pass pass no yes no
218 chapter 11 prom mode byte programming mode timing program program verify a0 to a16 d0 to d7 +12.5 v v dd v pp address input hi-z hi-z data input data output hi-z +6.5 v v dd v dd ce (input) pgm (input) oe (input)
219 chapter 11 prom mode 11.4 prom read procedure the contents of the prom are read to the external data bus (d0 to d7) in the following procedure: (1) fix mode0 = l, and mode1 = l. connect the unused pins as described in 1.5.2 prom programming mode . (2) supply +5 v to the v dd and v pp pins. (3) input the address of the data to be read to the a0 to a16 pins. (4) read mode (ce = l, oe = l) (5) the data is output to the d0 to d7 pins. figure 11-1 shows the timing of (2) to (5) above. figure 11-1. prom read timing a0 to a16 address input hi-z data output ce (input) oe (input) hi-z d0 to d7
220 chapter 11 prom mode 11.5 screening of otprom version the one-time-programmable rom (otprom) version, m pd70p3002gc-7ea, cannot be completely tested by nec before shipment. it is recommended to perform screening to verify the prom after the prom has been stored under the following conditions: storage temperature storage time 125 c 24 hours 11.6 caution on stop mode release when using external clock when using the external clock, the clock supply is controlled by an external system. therefore, when releasing the stop mode (released by reset or nmi input), restart the clock supply more than 150 m s before reset or nmi input to secure the prom stabilization time.
221 appendix a register index appendix a register index symbol name unit page asim00 asynchronous serial interface mode register 00 uart 151 asim01 asynchronous serial interface mode register 01 uart 153 asis0 asynchronous serial interface status register 0 uart 154 bcc bus cycle control register bcu 56 bprm0 baud rate generator prescaler mode register 0 brg0 176 bprm1 baud rate generator prescaler mode register 1 brg1 176 brg0 baud rate generator register 0 brg0 176 brg1 baud rate generator register 1 brg1 176 cc10 capture/compare register 10 rpu 119 cc11 capture/compare register 11 rpu 119 cc12 capture/compare register 12 rpu 119 cc13 capture/compare register 13 rpu 119 cm4 compare register 4 rpu 120 cmic4 interrupt control register intc 83 csic0 interrupt control register intc 83 csic1 interrupt control register intc 83 csic2 interrupt control register intc 83 csim0 clocked serial interface mode register 0 csi0 164 csim1 clocked serial interface mode register 1 csi1 164 csim2 clocked serial interface mode register 2 csi2 164 dwc data wait control register bcu 54 ecr interrupt source register cpu 30 eipc interrupt status save register cpu 30 eipsw interrupt status save register cpu 30 fepc nmi status save register cpu 30 fepsw nmi status save register cpu 30 intm0 external interrupt mode register 0 intc 73 intm1 external interrupt mode register 1 intc 84 intm2 external interrupt mode register 2 intc 84 ispr in-service priority register intc 85 mm memory expansion mode register port 46 ovic1 interrupt control register intc 83 p0 port 0 port 182 p1 port 1 port 186 p2 port 2 port 187
222 appendix a register index symbol name unit page p3 port 3 port 192 p4 port 4 port 197 p5 port 5 port 199 p6 port 6 port 201 p9 port 9 port 202 p10 port 10 port 205 p0ic0 interrupt control register intc 83 p0ic1 interrupt control register intc 83 p0ic2 interrupt control register intc 83 p0ic3 interrupt control register intc 83 p1ic0 interrupt control register intc 83 p1ic1 interrupt control register intc 83 p1ic2 interrupt control register intc 83 p1ic3 interrupt control register intc 83 pm0 port 0 mode register port 184 pm1 port 1 mode register port 187 pm2 port 2 mode register port 191 pm3 port 3 mode register port 195 pm4 port 4 mode register port 198 pm5 port 5 mode register port 200 pm6 port 6 mode register port 202 pm9 port 9 mode register port 204 pm10 port 10 mode register port 207 pmc0 port 0 mode control register port 185 pmc2 port 2 mode control register port 192 pmc3 port 3 mode control register port 196 pmc10 port 10 mode control register port 207 prcmd command register cg 103 psc power save control register cg 101 psw program status word cpu 31,73,85,88 rxb0 receive buffer 0 uart 155 rxb0l receive buffer 0l uart 155 seic0 interrupt control register intc 83 sio0 serial i/o shift register 0 csi0 165 sio1 serial i/o shift register 1 csi1 165 sio2 serial i/o shift register 2 csi2 165 sric0 interrupt control register intc 83
223 appendix a register index symbol name unit page stic0 interrupt control register intc 83 sys system status register cg 98, 103 tm1 timer 1 rpu 118 tm4 timer 4 rpu 120 tmc1 timer control register 1 rpu 123 tmc4 timer control register 4 rpu 124 toc1 timer output control register 1 rpu 125 tovs timer overflow status register rpu 126 tum1 timer unit mode register 1 rpu 121 txs0 transmit shift register 0 uart 156 txs0l transmit shift register 0l uart 156
224 appendix a register index [memo]
225 appendix b instruction set list appendix b instruction set list legend (1) symbols used for operand description symbol description reg1 general register (r0 to r31): used as source register reg2 general register (r0 to r31): mainly used as destination register immx x-bit immediate dispx x-bit displacement regld system register number bit#3 3-bit data for bit number specification ep element pointer (r30) cccc condition code vector 5-bit data specifying trap vector (00h-1fh) (2) symbols used for code symbol description r 1-bit data of code specifying reg1 or regid r 1-bit data of code specifying reg2 d 1-bit data of displacement i 1-bit data of immediate cccc 4-bit data for condition code specification bbb 3-bit data for bit number specification (3) symbols used for operation description symbol description <- assignment gr[ ] general register sr[ ] system register zero-extend (n) zero-extends n to word length sign-extend (n) sign-extends n to word length load-memory (a,b) reads data of size b from address a store-memory (a,b,c) writes data b of size c to address a load-memory-bit (a,b) reads bit b of address a store-memory-bit (a,b,c) writes c to bit b of address a saturated (n) performs saturated processing of n (n is 2s complement). if n is n 3 7fffffffh as result of calculation, 7fffffffh. if n is n 80000000h as result of calculation, 80000000h. result reflects result on flag byte byte (8 bits)
226 appendix b instruction set list symbol description halfword half-word (16 bits) word word (32 bits) + add C subtract || bit concatenation x multiply ? divide and logical product or logical sum xor exclusive logical sum not logical negate logically shift left by logical left shift logically shift right by logical right shift arithmetically shift right by arithmetic right shift (4) symbols used for execution clock description symbol description i : issue to execute another instruction immediately after instruction execution r : repeat to execute same instruction immediately after instruction execution l : latency to reference result of instruction execution by the next instruction (5) symbols used for flag operation identifier description (blank) not affected 0 cleared to 0 x set or cleared according to result r previously saved value is restored
227 appendix b instruction set list condition code v 0 0 0 0 ov = 1 overflow nv 1 0 0 0 ov = 0 no overflow c/l 0 0 0 1 cy = 1 carry lower (less than) nc/nl 1 0 0 1 cy = 0 no carry no lower (greater than or equal) z/e 0 0 1 0 z = 1 zero equal nz/ne 1 0 1 0 z = 0 not zero not equal nh 0 0 1 1 (cy or z) = 1 not higher (less than or equal) h 1 0 1 1 (cy or z) = 0 higher (greater than) n 0 1 0 0 s = 1 negative p 1 1 0 0 s = 0 positive t 0 1 0 1 always (unconditional) sa 1 1 0 1 sat = 1 saturated lt 0 1 1 0 (s xor ov) = 1 less than signed ge 1 1 1 0 (s xor ov) = 0 greater than or equal signed le 0 1 1 1 ((s xor ov) or z) = 1 less than or equal signed gt 1 1 1 1 ((s xor ov) or z) = 0 greater than signed condition name (cond) condition code (cccc) conditional expression description
228 appendix b instruction set list instruction set (alphabetical order) (1/4) irlcyovsz sat add reg1, reg2 gr[reg2]<-gr[reg2]+gr[reg1] 1 1 1 x x x x imm5, reg2 gr[reg2]<-gr[reg2]+sign-extend(imm5) 1 1 1 x x x x addi imm16, reg1, reg2 gr[reg2]<-gr[reg1]+sign-extend(imm16) 1 1 1 x x x x and reg1, reg2 gr[reg2]<-gr[reg2]and gr[reg1] 1 1 1 0 x x andi imm16, reg1, reg2 gr[reg2]<-gr[reg1]and zero-extend(imm16) 1 1 1 0 0 x bcond disp9 if conditions are satisfied 3 3 3 then pc<-pc+sign-extned(disp9) 1 1 1 clr1 bit#3, disp16[reg1] adr<-gr[reg1]+sign-extend(disp16) 4 4 4 x z flag<-not(load-memory-bit(adr, bit#3)) store-memory-bit(adr, bit#3.0) cmp reg1, reg2 result<-gr[reg2]Cgr[reg1] 1 1 1 x x x x imm5, reg2 result<-gr[reg2]Csign-extend(imm5) 1 1 1 x x x x di psw.id<-1 1 1 1 (maskable interrupt disabled) divh reg1, reg2 gr [reg2]<-gr [reg2] ? gr [reg1] note2 36 36 36 x x x (signed division) ei psw.id<-0 1 1 1 (maskable interrupt enabled) halt stops 1 1 1 jarl disp22, reg2 gr[reg2]<-pc+4 3 3 3 pc<-pc+sign-extend(disp22) jmp [reg1] pc<-gr[reg1] 3 3 3 jr disp22 pc<-pc+sign-extend(disp22) 3 3 3 ld.b disp16[reg1], reg2 adr<-gr[reg1]+sign-extend(disp16) 1 1 2 gr[reg2]<-sign-extend(load-memory(adr, byte)) ld.h disp16[reg1], reg2 adr<-gr[reg1]+sign-extend(disp16) 1 1 2 gr[reg2]sign-extend(load-memory(adr, halfword)) ld.w disp16p[reg1], reg2 adr<-gr[reg1]+sign-extend(disp16) 1 1 2 gr[reg2]<-load-memory(adr, word) notes 1. dddddddd is the higher 8 bits of disp9. 2. only the lower half-word is valid. 3. ddddddddddddddddddddd is the higher 21 bits of disp22. 4. ddddddddddddddd is the higher 15 bits of disp16. operation execution clock mnemonic operand code when condition satisfied when condition not satisfied 10bbb111110rrrrr dddddddddddddddd rrrrr001111rrrrr rrrrr010011i ii i i 0000011111100000 0000000101100000 rrrrr000010rrrrr 1000011111100000 0000000101100000 0000011111100000 0000000100100000 r r r r r 11110dddddd ddddddddddddddd0 note 3 00000000011rrrrr 0000011110dddddd ddddddddddddddd0 note 3 rrrrr111000rrrrr dddddddddddddddd rrrrr111001rrrrr ddddddddddddddd0 note 4 rrrrr111001rrrrr ddddddddddddddd1 note 4 r r r r r 001110rrrrr r r r r r 010010 i i i i i r r r r r 110000rrrrr iiiiiiiiiiiiiiii r r r r r 001010rrrrr r r r r r 110110rrrrr iiiiiiiiiiiiiiii ddddd1011dddcccc note 1 flag
229 appendix b instruction set list instruction set (alphabetical order) (2/4) irlcyovsz sat ldsr reg2, regid sr[regid]<-gr[reg2] regid = eipc, fepc 1 1 3 regid = eipsw, fepsw 1 regid = psw 1 xxxx x mov reg1, reg2 gr[reg2]<-gr[reg1] 1 1 1 imm5, reg2 gr[reg2]<-sign-extend(imm5) 1 1 1 movea imm16, reg1, reg2 gr[reg2]<-gr[reg1]+sign-extend(imm16) 1 1 1 movhi imm16, reg1, reg2 gr[reg2]<-gr[reg1]+(imm16 || 0 16 ) 111 mulh reg1, reg2 gr[reg2]<-gr[reg2] note2 xgr[reg1] note2 112 (signed multiplication) imm5, reg2 gr[reg2]<-gr[reg2] note2 xsign-extend(imm5) 1 1 2 (signed multiplication) mulhi imm16, reg1, reg2 gr[reg2]<-gr[reg1] note2 ximm16 1 1 2 (signed multiplication) nop uses 1 clock cycle without doing anything 1 1 1 not reg1, reg2 gr[reg2]<-not(gr[reg1]) 1 1 1 0 x x not1 bit#3, disp16[reg1] adr<-gr[reg1]+sign-extend(disp16) 4 4 4 x z flag<-not(load-memory-bit(adr, bit#3)) store-memory-bit(adr, bit#3, z flag) or reg1, reg2 gr[reg2]<-gr[reg2]or gr[reg1] 1 1 1 0 x x ori imm16, reg1, reg2 gr[reg2]<-gr[reg1]or zero-extend(imm16) 1 1 1 0 x x reti if psw.ep = 1 4 4 4 r r r r r then pc <-eipc psw <-eipsw else if psw.np = 1 then pc <-fepc psw <-fepsw else pc <-eipc psw <-eipsw sar reg1, reg2 gr[reg2]<-gr[reg2]arithmetically shift right 1 1 1 x 0 x x by gr[reg1] imm5, reg2 gr[reg2]<-gr[reg2]arithmetically shift right 1 1 1 x 0 x x by zero-extend(imm5) notes 1. the op code of this instruction uses the field of reg1 though the source register is shown as reg2 in the above table. therefore, the meaning of register specification for mnemonic description and op code is different from that of the other instructions. rrrrr = regid specification rrrrr = reg2 specification 2. only the lower half-word data is valid. operation execution clock mnemonic operand code r r r r r 111111rrrrr 0000000000100000 note 1 r r r r r 000000rrrrr r r r r r 010000 i i i i i r r r r r 110001rrrrr iiiiiiiiiiiiiiii r r r r r 110010rrrrr iiiiiiiiiiiiiiii r r r r r 000111rrrrr r r r r r 010111 i i i i i r r r r r 110111rrrrr iiiiiiiiiiiiiiii 0000000000000000 r r r r r 000001rrrrr 01bbb111110rrrrr dddddddddddddddd r r r r r 001000rrrrr r r r r r 110100rrrrr iiiiiiiiiiiiiiii 0000011111100000 0000000101000000 r r r r r 111111rrrrr 0000000010100000 r r r r r 010101 i i i i i flag
230 appendix b instruction set list rrrrr000110rrrrr rrrrr010001ii i ii rrrrr000101rrrrr rrrrr110011rrrrr iiiiiiiiiiiiiiii rrrrr000100rrrrr r r r r r 1111110cccc 0000000000000000 00bbb111110rrrrr dddddddddddddddd rrrrr111111rrrrr 0000000011000000 rrrrr010110ii i ii rrrrr111111rrrrr 0000000010000000 rrrrr010100ii i ii r r r r r 0110ddddddd r r r r r 1000ddddddd note 1 r r r r r 1010dddddd0 note 2 r r r r r 0111ddddddd r r r r r 1001ddddddd note 1 r r r r r 1010dddddd1 note 2 rrrrr111010rrrrr dddddddddddddddd instruction set (alphabetical order) (3/4) irlcyovsz sat satadd reg1, reg2 gr[reg2]<-saturated(gr[reg2]+gr[reg1]) 1 1 1 xxxx x imm5, reg2 gr[reg2]<-saturated(gr[reg2]+sign-extend(imm5)) 1 1 1 xxxx x satsub reg1, reg2 gr[reg2]<-saturated(gr[reg2]Cgr[reg1]) 1 1 1 xxxx x satsubi imm16, reg1, reg2 gr[reg2]<-saturated(gr[reg1]Csign-extend(imm16)) 1 1 1 xxxx x satsubr reg1, reg2 gr[reg2]<-saturated(gr[reg1]Cgr[reg2]) 1 1 1 xxxx x setf cccc, reg2 if conditions are satisfied 1 1 1 then gr[reg2]<-00000001h else gr[reg2]<-00000000h set1 bit#3, disp16[reg1] adr<-gr[reg1]+sign-extend(disp16) 4 4 4 x z flag<-not(load-memory-bit(adr, bit#3)) store-memory-bit(adr, bit#3, 1) shl reg1, reg2 gr[reg2]<-gr[reg2] logically shift left by gr[reg1] 1 1 1 x 0 x x imm5, reg2 gr[reg2]<-gr[reg1] logically shift left by 1 1 1 x 0 x x zero-extend(imm5) shr reg1, reg2 gr[reg2]<-gr[reg2] logically shift right by gr[reg1] 1 1 1 x 0 x x imm5, reg2 gr[reg2]<-gr[reg2] logically shift right by 1 1 1 x 0 x x zero-extend(imm5) sld.b disp7[ep], reg2 adr<-ep+zero-extend(disp7) 1 1 2 gr[reg2]<-sign-extend(load-memory(adr, byte)) sld.h disp8[ep], reg2 adr<-ep+zero-extend(disp8) 1 1 2 gr[reg2]<-sign-extend(load-memory(adr, halfword)) sld.w disp8[ep], reg2 adr<-ep+zero-extend(disp8) 1 1 2 gr[reg2]<-load-memory(adr, word) sst.b reg2, disp7[ep] adr<-ep+zero-extend(disp7) 1 1 1 store-memory(adr, gr[reg2], byte) sst.h reg2, disp8[ep] adr<-ep+zero-extend(disp8) 1 1 1 store-memory(adr, gr[reg2], halfword) sst.w reg2, disp8[ep] adr<-ep+zero-extend(disp8) 1 1 1 store-memory(adr, gr[reg2], word) st.b reg2, disp16[reg1] adr<-gr[reg1]+sign-extend(disp16) 1 1 1 store-memory(adr, gr[reg2], byte) notes 1. ddddddd is the higher 7 bits of disp8. 2. dddddd is the higher 6 bits of disp8. operation execution clock mnemonic operand code flag
231 appendix b instruction set list instruction set (alphabetical order) (4/4) irlcyovsz sat st.h reg2, disp16[reg1] adr<-gr[reg1]+sign-extend(disp16) 1 1 1 store-memory(adr, gr[reg2], halfword) st.w reg2, disp16[reg1] adr<-gr[reg1]+sign-extend(disp16) 1 1 1 store-memory(adr, gr[reg2], word) stsr regid, reg2 gr[reg2]<-sr[regid] 1 1 1 sub reg1, reg2 gr[reg2]<-gr[reg2]Cgr[reg1] 1 1 1 xxxx subr reg1, reg2 gr[reg2]<-gr[reg1]Cgr[reg2] 1 1 1 xxxx trap vector eipc <-pc+4(restored pc) 4 4 4 eipsw <-psw ecr.eicc <-interrupt code psw.ep <-1 psw.id <-1 pc <-00000040h(vector = 00h-0fh) 00000050h(vector = 10h-1fh) tst reg1, reg2 result<-gr[reg2] and gr[reg1] 1 1 1 0 x x tst1 bit#3, disp16[reg1] adr<-gr[reg1]+sign-extend(disp16) 3 3 3 x z flag<-not(load-memory-bit(adr, bit#3)) xor reg1, reg2 gr[reg2]<-gr[reg2] xor gr[reg1] 1 1 1 0 x x xori imm16, reg1, reg2 gr[reg2]<-gr[reg1] xor zero-extend(imm16) 1 1 1 0 x x note ddddddddddddddd is the higher 15 bits of disp16. operation execution clock mnemonic operand code r r r r r 111011rrrrr ddddddddddddddd0 note r r r r r 111011rrrrr ddddddddddddddd1 note r r r r r 111111rrrrr 0000000001000000 r r r r r 001101rrrrr r r r r r 001100rrrrr 00000111111 i i i i i 0000000100000000 r r r r r 001011rrrrr 11bbb111110rrrrr dddddddddddddddd r r r r r 001001rrrrr r r r r r 110101rrrrr iiiiiiiiiiiiiiii flag
232 appendix b instruction set list [memo]
233 appendix c index appendix c index [a] a0 to a16 ........................................................ 23 a16 to a23 ...................................................... 19 ad0 to ad7 ..................................................... 18 ad8 to ad15 ................................................... 18 address space .................................... 34, 35, 47 alv10, alv11 .............................................. 125 application fields .............................................. 3 asim00, asim01 .......................................... 151 asis0 ............................................................ 154 assembler reservation register ...................... 29 astb ............................................................... 20 asynchronous serial interface ...................... 148 status register 0 ............................. 154 mode register 00, 01 ..................... 151 [b] basic operation (serial interface function) ... 166 baud rate generator 0, 1 ................................ 173 generator register 0, 1 ................... 176 generator prescaler mode register 0, 1 .................................... 176 bcc ................................................................. 56 bcn1 (n = 0 to 7) ........................................... 56 bcu ................................................................... 8 boundary operation condition ........................ 64 bprm0, bprm1 ........................................... 176 bprm0 to bprm2 (m = 0, 1) ...................... 176 brce0, brce1 ............................................ 176 brg0, brg1 ................................................ 176 brg set data ................................................ 174 bus control function ................................. 51 control pin ......................................... 51 control unit .......................................... 8 cycle control register ........................ 56 hold ............................................. 57, 64 priority ............................................... 65 timing ................................................ 58 byte write mode .............................................. 214 [c] capture operation ......................................... 130 capture/compare register 10 to 13 ............. 119 cc10 to cc13 .............................................. 119 ce ................................................................... 23 ce1 ............................................................... 123 ce4 ............................................................... 124 ces10, ces11 ............................................. 121 cesel .......................................................... 101 cg ..................................................................... 8 cksel ............................................................ 21 cl0 ................................................................ 152 clkout .......................................................... 21 clock generation function .......................... 95 generator ............................................ 8 output control ................................. 113 output inhibit ............................. 99, 113 clocked serial interface 0 to 2 ..................... 162 clocked serial interface mode register 0 to 2 ..... 164 clsn1, clsn0 (n = 0 to 2) .......................... 164 cm4 ............................................................... 120 cmic4 ............................................................. 83 cmif4 ............................................................. 83 cmmk4 ........................................................... 83 cmpr40 to cmpr42 ..................................... 83 cms10 to cms 13 ....................................... 122 command register ........................................ 103 compare operation (timer 1) ....................... 132 compare operation (timer 4) ........................ 135 compare register 4 ...................................... 120 connection of unused pins ............................ 24 control register ............................................. 101 count clock selection (timer 1) .................... 127 count operation (timer 1) ............................. 127 count operation (timer 4) ............................. 134 cpu ................................................................... 8 address space .................................. 34 function ............................................. 27 register set ....................................... 28 crxe0 to crxe2 ........................................ 164 csi system configuration ............................. 172 csic0 to csic2 ............................................. 83 csif0 to csif2 .............................................. 83 csim0 to csim2 .......................................... 164 csmk0 to csmk2 .......................................... 83 csi0 to csi2 ................................................. 162 csot0 to csot2 ........................................ 164
234 appendix c index csprn0 to csprn2 (n = 0 to 2) .................. 83 ctxe0 to ctxe2 ......................................... 164 cv dd ................................................................................................. 22 cv ss ................................................................ 22 cy ................................................................... 31 cycle measurement ..................................... 143 [d] d0 to d7 .......................................................... 23 data space .......................................... 36, 47, 65 data wait control register ............................... 54 dclk0, dclk1 ............................................. 101 direct mode .................................................... 96 dstb ............................................................... 20 dwc ................................................................ 54 dwn0 to dwn1 (n = 0 to 7) ............................ 54 [e] ebs0 ............................................................. 153 eclr1 ........................................................... 121 ecr ................................................................. 30 eicc ................................................................ 30 eipc ................................................................ 30 eipsw ............................................................. 30 element pointer .............................................. 29 ento10, ento11 ........................................ 125 ep .............................................................. 31, 88 es0n0, es0n1 (n = 0 to 3) ............................ 84 es1n0, es1n1 (n = 0 to 3) ............................ 84 esn0 ............................................................... 73 eti ................................................................. 123 exception processing function .......................... 67 table .................................................. 38 trap ................................................... 88 external count clock ..................................... 128 external expansion mode .............................. 45 external interrupt mode register 0 ................................ 73 mode register 1 ................................ 84 mode register 2 ........................ 84, 125 external memory area .................................... 42 external wait function ..................................... 55 [f] fe0 ................................................................ 154 fecc ............................................................... 30 fepc ............................................................... 30 fepsw ........................................................... 30 function block configuration ............................ 7 [g] general register .............................................. 29 global pointer ................................................. 29 [h] halt mode ............................................. 99, 104 hldak ............................................................ 21 hldrq ............................................................ 21 [i] ic0 ................................................................... 22 id ............................................................... 31, 85 idle .............................................................. 101 idle state insertion function ............................ 56 ilgop ............................................................. 68 illegal op code ................................................ 88 ims10 ims13 ................................................ 122 initial register values .................................... 213 initialize ......................................................... 210 input clock selection (clock generator) .......... 96 input clock selection (timer 4) ...................... 134 intc .................................................................. 8 intcm4 ........................................................... 68 intcsi0 to intcsi2 ....................................... 68 internal block diagram ..................................... 7 count clock ..................................... 127 peripheral i/o interface .................... 66 ram area ......................................... 40 rom/prom area ............................. 38 units .................................................... 8 interrupt controller ............................................. 8 control register ................................. 82 latency time ...................................... 93 list ..................................................... 68 processing (service) ......................... 67 request ............................................ 157 stack pointer ..................................... 29 source register ................................. 30 table .................................................. 38 interval timer ................................................. 137 intm0 ............................................................. 73 intm1 ............................................................. 84 intm2 ..................................................... 84, 125
235 appendix c index intov1 ........................................................... 68 intp00 to intp03 .................................... 17, 68 intp10 to intp13 .......................................... 16 intpn/intccn (n = 10 to 13) ........................ 68 intser0 ......................................................... 68 intsr0 ........................................................... 68 intst0 ............................................................ 68 ispr (in-service priority register) .................. 85 ispr0 to ispr7 .............................................. 85 [l] lben ............................................................... 19 link pointer ..................................................... 29 [m] maskable interrupt .................................... 74, 78 status flag ......................................... 85 memory block function ................................... 53 expansion mode register ................. 46 map ............................................. 37, 48 read .................................................. 58 write .................................................. 62 mm .................................................................. 46 mm0 to mm3 ................................................... 46 mode0, mode1 ............................................ 22 mod0 to mod2 ............................................ 164 multiple interrupt ............................................. 91 [n] nmi ............................................................ 17, 68 noise elimination circuit ............................... 208 normal operation mode ........................ 4, 11, 16 note (timer/counter function) ....................... 145 np ............................................................. 31, 73 number of access clock ................................. 52 [o] oe ................................................................... 23 operation mode .............................................. 32 ordering information ......................................... 3 ost ............................................................... 121 output disable mode .................................... 214 ov ................................................................... 31 ove0 ............................................................. 154 overflow (timer 1) ......................................... 128 overflow (timer 4) ......................................... 134 ovf1, ovf4 ................................................. 126 ovic1 ............................................................. 83 ovif1 .............................................................. 83 ovmk1 ............................................................ 83 ovpr10 to ovpr12 ...................................... 83 [p] p0ic0 to p0ic3 .............................................. 83 p0if0 to p0if3 ............................................... 83 p0mk0 to p0mk3 ........................................... 83 p0pr00 to p0pr02 ........................................ 83 p0pr10 to p0pr12 ........................................ 83 p0pr20 to p0pr22 ........................................ 83 p0pr30 to p0pr32 ........................................ 83 p1ic0 to p1ic3 .............................................. 83 p1if0 to p1if3 ............................................... 83 p1mk0 to p1mk3 ........................................... 83 p1prn0 to p1prn2 (n = 0 to 3) .................... 83 page data latch mode .................................. 214 page write mode .......................................... 214 pc ................................................................... 29 pe0 ................................................................ 154 period where interrupt is not acknowledged ..... 93 peripheral i/o area ......................................... 41 peripheral i/o register .................................... 49 pgm ................................................................ 23 pin configuration ............................................... 4 pin function ............................................... 11, 16 pin i/o circuit .................................................. 25 pin status ........................................................ 15 pll mode ........................................................ 96 pll stabilization ............................................. 98 pllsel ........................................................... 21 port ............................................................ 9, 179 port 0 (p0) .................................................... 182 block diagram of p00 and p01 ..... 183 block diagram of p02 to p07 ......... 183 p00 to p07 ............................... 16, 182 port 0 mode control register (pmc0) .......... 185 pmc00 to pmc07 .......................... 185 port 0 mode register (pm0) ......................... 184 pm00 to pm07 ............................... 184 port 1 (p1) .................................................... 186 block diagram of p10 to p17 ......... 186 p10 to p17 ............................... 16, 186 port 1 mode register (pm1) ......................... 187 pm10 to pm17 ............................... 187 port 10 (p10) ................................................ 205
236 appendix c index block diagram of p100 and p103 .... 207 block diagram of p101 ................... 208 block diagram of p102 ................... 208 p100 to p103 ........................... 21, 207 port 10 mode control register (pmc10) ...... 209 pmc100 and pmc101 ................... 209 port 10 mode register (pm10) ..................... 209 pm100 to pm103 ........................... 209 port 2 (p2) .................................................... 187 block diagram of p20 ..................... 188 block diagram of p21 to p24 ......... 188 block diagram of p25 ..................... 189 block diagram of p26 ..................... 189 block diagram of p27 ..................... 190 p20 to p27 ............................... 16, 187 port 2 mode control register (pmc2) .......... 192 pmc21 to pmc27 .......................... 192 port 2 mode register (pm2) ......................... 191 pm21 to pm27 ............................... 191 port 3 (p3) .................................................... 192 block diagram of p30, p33, p35 ... 193 block diagram of p31 and p36 ..... 194 block diagram of p32 and p37 ..... 194 block diagram of p34 ..................... 195 p30 to p37 ............................... 17, 192 port 3 mode control register (pmc3) .......... 196 pmc30 to pmc37 .......................... 196 port 3 mode register (pm3) ......................... 195 pm30 to pm37 ............................... 195 port 4 (p4) .................................................... 197 block diagram of p40 to p47 ... 18, 197 p40 to p47 ..................................... 197 port 4 mode register (pm4) ......................... 198 pm40 to pm47 ............................... 198 port 5 (p5) .................................................... 199 block diagram of p50 to p57 ......... 199 p50 to p57 ............................... 18, 199 port 5 mode register (pm5) ......................... 200 pm50 to pm57 ............................... 200 port 6 (p6) .................................................... 201 block diagram of p60 to p67 ......... 201 p60 to p67 ............................... 19, 201 port 6 mode register (pm6) ......................... 202 pm60 to pm67 ............................... 202 port 9 (p9) .................................................... 202 block diagram of p90 to p97 ......... 203 p90 to p97 ............................... 19, 202 port 9 mode register (pm9) ......................... 204 pm90 to pm97 ............................... 204 power save control ......................................... 99 power save control register ......................... 101 power save mode operation .......................... 56 prcmd ......................................................... 103 prerr .......................................................... 103 priority control ................................................. 91 priority of interrupt and exception ................. 91 prm11 .......................................................... 123 prm40, prm41 ............................................ 124 program counter ............................................. 29 program inhibit mode ................................... 214 program register set ....................................... 29 program space ................................... 36, 47, 65 program status word (psw) ....... 31, 73, 85, 88 program verify mode .................................... 214 programmable wait function .......................... 54 prom ............................................................... 8 prom mode ................................................. 213 prom programming mode .................. 6, 14, 23 prom read mode .......................................... 32 prom read procedure ................................. 219 prom write procedure ................................. 215 prs10, prs11 ............................................. 123 prs40 ........................................................... 124 ps00, ps01 .................................................. 152 psc ............................................................... 101 pulse width measurement ............................ 138 pwm output .................................................. 140 [r] r0 to r31 .......................................................... 29 r/w ................................................................. 20 ram .................................................................. 8 read mode ................................................... 213 real-time pulse unit ................................. 8, 115 receive buffer 0, 0l ..................................... 155 reception completion interrupt .................... 157 receive error interrupt ................................. 157 reg0 to reg7 ............................................. 103 reset ............................................................ 22 reset ............................................................ 68 reset function ............................................... 211 reti instruction operation .......... 72, 77, 87, 90 rfu ................................................................. 31 rom .................................................................. 8 rom-less mode .............................................. 32
237 appendix c index rpu ........................................................... 8, 116 rxb00 to rxb07 .......................................... 155 rxb0, rxb0l ............................................... 155 rxd ................................................................. 18 rxe0 ............................................................. 151 rxeb0 .......................................................... 155 [s] s ...................................................................... 31 sat ................................................................. 31 sck0 ............................................................... 17 sck1 ............................................................... 17 sck2 ............................................................... 17 scls0 ........................................................... 153 screening of otprom version ................... 222 seic0 .............................................................. 83 seif0 .............................................................. 83 semk0 ............................................................ 83 sepr00 to sepr02 ....................................... 83 serial i/o shift register 0 to 2 ...................... 165 serial interface ........................................ 10, 147 si0 to si2 ........................................................ 17 single-chip mode ............................................ 32 sio .................................................................... 8 sio0 to sio2 ................................................ 165 sion0 to sion7 (n = 0 to 2) ........................ 165 sl0 ................................................................ 152 so0 to so2 .................................................... 17 software exception ......................................... 86 software stop mode ............................ 99, 108 sot0 ............................................................. 154 specifing oscillation stabilization time ......... 110 sric0 .............................................................. 83 srif0 .............................................................. 83 srmk0 ............................................................ 83 srpr00 to srpr02 ...................................... 83 st0, st1 ......................................................... 20 stack pointer ................................................... 29 standby mode ............................................... 214 status transition ............................................ 100 stic0 .............................................................. 83 stif0 .............................................................. 83 stmk0 ............................................................ 83 stor00 to stpr02 ....................................... 83 stp ............................................................... 101 sys ......................................................... 98, 102 system register set ........................................ 30 [t] tbc ............................................................... 112 tbcs ............................................................. 101 tclr1 ............................................................. 16 tes10 and tes11 ....................................... 121 text pointer ..................................................... 29 ti1 ................................................................... 16 time base counter ........................................ 112 timer /counter function ............................ 115 control register 1 ............................ 123 control register 4 ............................ 124 output control register 1 ................ 125 overflow status register ................. 126 unit mode register 1 ....................... 121 timer 1 .......................................................... 118 timer 1 operation ......................................... 127 timer 4 .......................................................... 120 timer 4 operation ......................................... 134 timing of 3-wire serial i/o mode .... 168, 169, 171 tm1 ............................................................... 118 capture operation example ............ 130 compare operation example .......... 132 tm4 ............................................................... 120 tmc1 ............................................................. 123 tmc4 ............................................................. 124 to10, to11 .................................................... 16 toc1 ............................................................. 125 tovs ............................................................ 126 transmission completion interrupt ............... 157 transmit shift register 0, 0l ......................... 156 trap0n, trap1n (n = 0 to f) ...................... 68 tum1 ............................................................. 121 txd ................................................................. 17 txed0 ........................................................... 156 txs0, txs0l ................................................ 156 txs00 to txs07 .......................................... 156 [u] uart ............................................................. 148 uben .............................................................. 19 unlock ......................................................... 98 [v] v dd ................................................................... 23 v pp ................................................................... 23 v ss ................................................................... 23
238 appendix c index [w] wait ............................................................... 22 wrap-around ............................................. 36, 47 wait function ................................................... 54 wait state inserting example ......................... 55 [x] x1, x2 ............................................................. 22 [z] zero register ................................................... 29 [others] 100-pin plastic qfp .......................................... 3
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